We have found that it is a great challenge to bridge the gap between using CPUs/MUCs, their associated languages, tools and compilers and using FPGAs with their associated languages, tools and compilers. These are the types challenges that Valent F(x) hopes to alleviate and to eventually create an inviting and even enjoyable gateway for CPU users to experience and become proficient in using FPGAs.  We previously introduced the flexibility using LOGi virtual components as a tool when using FPGA and the Raspberry Pi together, we now would like to introduce another tool that we are working on that can potentially be a bridge that will allow CPU/MCU an easy way of creating, customizing and compiling hardware description language code without ever needing to write a line of code. 

One of the challenges of working with FPGA’s is the very very very large tools required to be installed on your PC to build/compile your custom HDL projects for the FPGA to use. A second challenge is that many users who want to work with FPGAs are not ready to begin writing their own HDL code in order to create their own projects.  We thought that it would be nice to come up with a solution to nip both of these issues in the bud.  Wouldn’t it be nice to be able to customize and a compile your project directly from your Pi or Bone?  Wouldn’t it be great to customize and a compile your project without writing a line of HDL? 

Introducing the “Skeleton” - Web Based Architecture HDL Editor/Compiler

With the LOGi-Boards we not only want to deliver a board to experience FPGA programming, but we also want to deliver the tools that will ease the user experience. Aside from the libraries of drivers, components and software libraries, we wanted to propose a novel approach to the design of FPGA architecture. Our architecture editor is web-based (nothing to install) and allows users to connect the components of the LOGi-library in a wishbone architecture. The architecture creation is performed by instantiating the components and dragging connection between them. The tool can then be used to generate a zip file containing the vhdl of the architecture, a Makefile to compile the architecture (linux only) and a .xise file that can be loaded as a project using Xilinx tools. 

Aside from the architecture, we have designed a web-service that can be run on a local machine or on a server. This web-service can take the generated zip file and generate the FPGA configuration file using Xilinx tools. This allows users to edit an architecture directly on the Raspberry Pi/beaglebone and get the FPGA configuration file from the server. This could be used in a classroom or hackerspace context with only one PC on the network running Xilinx tools and people directly using their raspberry-pi/beaglebone to design an FPGA architecture.

This tool is still a work in progress but we validated the design flow up to the loading of the FPGA with the generated bit-file. There is still a lot to do to bring a hassle free experience (help from experienced javascript programmers could be useful) to the user but we are definitely on a good path.  For those that have javascript and web development experience and would like to help, please contact us at support@valentfx.com. 

Jonathan has put together a video overview of the GUI based HDL compilation process complete with loading the generated bitstream onto the FPGA from the Pi/Bone host after it is compiled in the “cloud”.  Have a look at the video overview on the LOGi Youtube Channel. 

Note that the Web compiler is strictly in beta at the moment and we have a lot of work to do before final implementation.  One of our bigger concerns is that there may be complications in the terms of use of the Xilinx tools that would be running in the cloud.  We will be working out these details and hope to have a nice solution for mainstream use soon. 

For now you can experiment with the user beta user interface of the "Skeleton" Editor, customize an HDL project using the LOGi components using the GUI editor and export the corresponding HDL to your computer.  Note that we do have a dedicated server which we are able to pass the generated HDL project and it compiles and returns a .bit file to load onto the FPGA.  To pass the generated HDL project for the compilation process you would enter the "path to server" where the compilation tools are installed.  We will need to work out potential terms of use licensing with Xilinx before we make this available to our users.