mjones
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Hi @sanguine8082 It appears that he wiki instructions were still referring to installing the old loader which is not compatible with the LOGI Pi 2. I have updated the wiki to correctly make and install the V2 loader: git clone https://github…
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HI @nickw Thanks for pointing that out. I will add this to the accepted answer. I hope it's smooth sailing from here! I have also updated the wiki page with more detailed instructions for Pi-2: http://valentfx.com/wiki/index.php?title=LOG…
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Hi Amanda, The LOGI module is shipped with the Omnivision OV7670 camera sensor and the datasheet can be found here: http://www.voti.nl/docs/OV7670.pdf or you can get the latest drectly from omnivision after filling out their form: http://www.ovt…
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Thanks for you insights John. Nice work on your own JTAG loader! How fast were you able to get it to run? Were you using the FTDI->JTAG interface using the FTDI MPSSE? I believe the papilio loader is a wrapper that is upon the xc3sprog loade…
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Hi @peepo Very good question. I have the Xilinx USB II cable, Digilent HS2. I have found that the HS2 is actually more reliable than the Xilinx USB II for general programming of FPGA and flash. I don't use chipscope or EDK, but HS2 is supp…
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Great to hear!
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Hi @caro Sounds fun! You will want to have a look at the logi wishbone example in the repository to get a feel for how you might want to build the co-processing applicaiton. You can tie the accellerator to the wishbone bus which can then be eas…
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Hi @morrisford The instructions in the Pong Chu book for simulations work when using xilinx ISE. Pong has a really good overview of the basic constructs used in the simulation, which vary slightly between verilog and vhdl. Pong Chu Chapter…
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Ahhh, yes the done pin could be an issue. The schematic on your referenced link is unreadable for what Pin 22 is doing on the LCD. Do you know what pin 22 functions as on the LCD? What happens if you disconnect the pin 22 pin from your wire conn…
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Dang. Well it appears that it is not the FPGA pins that are the problem - other than possibly the PRGB pin. It could also be a pull-up/down on the board that is the problem which would be seen in the following "DC" test. Next step you would ne…
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Do not short pin1/2 of the JTAG header (J5) this shorts 3.3V to gnd. Short Pins 1/2 of P6 as shown in the image. What happens with the LCD when you do this?
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It is hard to say what the current problem is. It might be possible to run things but it will take careful inspections of pins states on the FPGA and the TFT display. Even if the pins are not being used on the TFT there may still be conflict wi…
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@jpiat which CS pin are you using to communicate with the FPGA? @peepo How will you use the FPGA if you cannot comunicate between the FPGA and the Rpi? The biggest killer here would be the shared use of the PRGB pin. It is the reset for the…
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HI @caro It appears that the cblas library should be able to build using gcc. They have a makfile in the download package they list here: http://www.netlib.org/blas/#_cblas You should be able to simply run the make file after transferring to…
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Yes, the chip did successfully program - then tries to configure itself, but fails of mode pin is not set correctly. The manual probably needs to be updated. I think the older version boards mode pins were defaul slave config. We have changed to…
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Hi @Randyrtx I am not sure why it would give this error. I just tested on my side with no problems using a digilent HS2 cable. Have you changed the MODE solder jumper on the bottom of the board? It should not be soldered for self config. …
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Hi @SquareOne We are making progress on the board with a newer version that will support daisy chained modules. We are not sure how we are going to release the cameras at this point along with some other new product. I can give you design files i…
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The previous linked image was actually for the V1 boards. I have updated it to the new image which supports the V2 board. http://valentfx.com/doc/logi-image/logibone/logibone_150429_ubuntu-14.04-console-armhf-2014-08-13.img.zip Note that I ju…
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Keeps us posted on your experience - hope the new changes come in handy. Keep us posted if we miss any of the needed documentation. Cheers!
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Hi Matt, Sorry for the confusion. And yes it is confusing! The R1.5.1 and V2 are the same. We were not aware E14 was going to call them V2 and the PCBs were already designed. I am making changes to documentation that will align with the E14 in…
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Looks good peepo! We have some older mechanical designs which we put in teh mechanical logi repo - most of which are outdated now: https://github.com/fpga-logi/logi-mechanical the current LOGI-Pi design fits all of the Rpi variants and thus …
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Thanks for sharing peepo. Indeed synthesizing code into hardware has many more pitfalls and requires more attentions to the coding/synthesis process that that of software (generally speaking). A good podcast I just finished listening to from em…
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@peepo Thanks for the update!
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Jonathan has created new images with updated loader for the "V2" LOGI boards. The images are backwards compatible with the V1 boards as well. We will be updating the links in the wiki as well. PS Seeed studio has stated that they shipped the f…
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Hi @peepo Sorry I overlooked that the project was spartan3 specific. The example he was using utilizes all of the spartan3 primitives and thus cannot be built on the spartan 6. There is a spartan6 version of the picoblaze/uart example proje…
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Here is the uart project that was linked on the gadget factory blog post:http://forum.gadgetfactory.net/index.php?/topic/2128-xilinx-vhdl-uart-example/#entry14616 Did you go through his linked youtube vidoes? Based upon the titles Jack walks y…