Hi Kumar,
You can find the sdram driver in the example sdram project on github:
https://github.com/fpga-logi/logi-projects/tree/master/logi-sdram-test/hw/common
Hope this helps.
Hi Trevor. Thanks for pointing this out. Attached is a pdf generated from AD16. It seems to be working correctly on my side. Let me know if it works for you and I will replace the one on github.
I tried loading with the logi-loader and had the same result as you.
I was able to successfully load the bitfile with a jtag loader using impact, so there may be something that conflicts with the SPI pins or perhaps there is an issue with the load…
Hi @socjcare
There is a setting under "Generate Programmging file" that allows you to set the done pin state once the bitstream is loaded. If set to "float" the LED would night be visible at all. See image.
If you have a jtag adapter you ca…
Hi @SoccerMichel . All of the latest "master" UCF files are kept in logi-hard (hardware) repository here:https://github.com/fpga-logi/logi-hard/tree/master/master_ucf/logi_pi
You will find the R1.5 ucf there.
Cheers.
Hi @socjcare Are you using the LOGI EDU board?
Yes all that you will need to do is to change LOC values for the differing pins on the LBone pmod pins that are connected to your VGA signals.
Here is possibly more user friendly guide to constr…
Hi @SoccerMichel Sorry to hear you are having trouble. I just tested teh cheapscope project build process on my version of 14.7 on Win, version P.21031013 and all went well.
Here are the stated supported devices for webpack:
http://www.xilinx…
@woolfel Sounds like a great job for the FPGA. It looks like you forgot to post your blog link
@jpiat specializes in image processing and has done a lot of work with the LOGI boards. He is probably the best person to take on this question as t…
Hi Peter,
The image processing app requires the use of a camera connected directly to the FPGA. We have used the LOGI Cam for this app, which can be purchased from us directly for $24. It uses a OV7670 camera module with a parallel interface. Un…
Glad you got it working @woolfel. I can't see how there is any way that the uart would conflict. I would guess that it must be with one of the upgraded packages using the "sudo apt-get dist-upgrade". We will work on getting an updated image that …
Hi @Kumar
The Lbone design shares some IO functions, based upon pin constraints and the number IO needed for all of the ports, etc. It is also assumed that GPMC is the main means of communication between the Lbone/BBB. That being the case, on th…
Hi Nakul,
This is not a very straight forward project for just starting, but could be possible with a lot of work. The problem is that it will require a great deal of understanding of computer architecture and knowing how to customize the HDL t…
As jpiat suggests, this is pretty sophisticated problem very specific to the BBB and not so much the FPGA. I am not sure I can be of much help here as I have only used the BBB in standard modes of operation.
Perhaps Jpiat has some more ideas. Ot…
Is this the state you are still working on: "Reset: The RST_n signal is used by the host for resetting the device, moving the device to the preidle state. By default, the RST_n signal is temporarily disabled in the device. The host must set ECSD reg…
The code for the servo using EDU is on the repo here:
https://github.com/fpga-logi/logi-projects/tree/master/logi-edu/logi-pi-nes-servo-pwm
The pantilt project your reference using BBOT was done by a LOGI user, Andy Gikling. His repo is here…
If you want to disable the emmc, why not just tie the emmc_RSTn signal low using with some solder points?
Based upon the schematics there is R162 which you you could permanently pull low (on the emmc side) by soldering to ground. This would ensu…
Hi @TySkby
Thanks for dropping by. Sorry for the confusion.
The LOGI bone primarily uses GPMC as the communication port between the FPGA and the BBB. On the BBB the GPMC port shares the same pins as the EMMC (BBB flash). Thus in order to…
The listed pins are in binary order. [M1:M0].
Where 01 is the M1:M0 needed for self config.
Therefore to setup Lpi R1.1.x for self config:
M1 = 0 and M0 = 1. Based upon the schematics for Lpi 1.1 M1 and M2 are pulled up to 3.3V by default (=…
If you are trying to boot from flash you must set the "mode" pins according to self configure mode. There are solder jumpers on the backside of the board which you can use to set to "self configure". The default mode is slave configure for the R1.…
Hi Peepo. Sorry I'm not going to be much help here as I have not used the xc3sprog. Maybe @jpiat or @johnbeetem or @Hamster has some experience with it?
One to note is that the flash change from
R0-R1.1 boards = M25PE16 (16Mbit flash)
R1.5. a…
Hi @hjalte
Have you run the "install_logibone.sh" to setup the eeprom with the correct device tree settings?
cd ~/logi-tools
sudo ./install_logibone.sh
Hi @Rjim781
It appears you are using an older version of the logi image that uses loader for V1 boards and won't work with the V2 (R1.5.1) boards. I have updated the wiki with a direct link to the latest image rather than to the directory of all…
Hi @Rjim781
Are you creating your own image or are you using the pre-built LOGI image?
The PI_VER=2 only needs to be used when building the loader for the Pi2. Otherwise you can leave this out of the make command and it will build by default…