jpiat
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Hi, we prototyped the interface between the logi-boards (pi and bone) and an MT9V034 camera sensor from Aptina and the communication was using LVDS at 300Mb/s. The interface was simplex (only data from camera to logi) and synchronous (one LVDS pai…
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Hi, i'll have a look at the project and see what can be wrong. At some point we worked on getting the wihsbone app working with SPI on the Logi-bone instead of GPMC and that is maybe where things were broken. Thanks for your feedback.
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Hi, there are very few difference between the two boards. The layout changed a bit but they share the same features. The version 2 is FCC/CE certified while the first version is not. Regards, Jonathan Piat
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Hi, good news, with your latest remarks, i built a new image based on 4.4 kernel that enables dynamic loading of overlays. The new image is not on the server yet, but pm me and i'll send a link for you to download and test. The image contains the …
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i had to change the name to txt, so you'll have to rename it to .json
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I have linked in an example file for skeleton with a single register that can be read/write. You can load it in skeleton through the browse at the top left of the window. Note that the register output is linked to its input. To get the memory addres…
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If you generate a project with a register in skeleton, the output and input of the register are not connected. If you want to be able to read the content you write, you need to connect the reg input to its output. I'll check why the wishbone app in …
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To have a better understanding at what the PWM example do, you have a look at the example project for our architecture editor, Skeleton : http://valentfx.com/skeleton/arch_editor.html?board=logibone In this demo we have the Beaglebone external mem…
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There is some existing work to map convolutional network trained in the caffe framework straight to FPGA logic. What you mention (only running the computer-vision on the FPGA) is a good idea, and could easily be performed in logic. One problem with …
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Hi, sorry for the late reply. The two commands that fails were used for the first version of the logibone were the write lock signal of the id eeprom was controlled by an i2c expander. Since the logibone overlay is loaded at boot, it had to be comp…
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When using the 14.04 image there should be no need to use the setup_device-tree script since the driver and device tree setup is performed on boot. Unfortunately instruction provided by Glen does not work with 14.04 images since device-tree support …
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Hi, i did something quite similar when we designed logi-face (). What i did at the time was to use a usb sound card and i soldered a wire to the the biased audio output on the USB dongle which was then wired to a MCP3008 connected to the FPGA over …
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You can sure the use the FPGA to binarize or compress the images before transferring to the CPU, but this depends on what your application needs. WIth the logi-pi, you cannot connect 4 camera because theres is not enough pins for four of the camera …
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The FPGA can process the image at high rate (for example doing sobel at 60fps is "easy") but transferring the image to the processor is not possible at high rate for the logi-pi. Other platforms like zedboard are more suitable for this kind of task.
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On the logipi the max bandwidth we get is 2MByte/s, a VGA image is 300kB, 4 camera would give 1.2MB so you can only expect ~1FPS ...
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Yes, it works fine !
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No idea of how plunify does it and if they have some partnership with Xilinx. The EULA of Xilinx for the web edition states that you can only use the tool for your personnal use which prevents us from giving access to cloud based tools.
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Hi, the wishbone_register module has a 16-bit output named reg_out. If you want to send to floating points values (32-bits), you will need 4 registers. When you write the floating point values to these registers, each floating poin value will be a…
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We have tested a prototype that is functional, but for now we failed to find an agreement with Xilinx to make the tool available to the public. We are still discussing with Xilinx on this to find a solution.
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The pin names declared in the ucf must match the name of the input/output ports of your pwm module. Can you copy paste the entity section of you pwm module for me to check ?
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What do you mean by call it in python ? If you want tobcommunicate from python with the hardware in the FPGA, you 'LL need to use a communication bus such as i2c, SPI or UART. In logi-projects we have designed a SPI to wishbone bus that allow us to …
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Here is a link to a quick study i did a while ago on myHDL and PSHDL : https://www.element14.com/community/groups/fpga-group/blog/2014/10/28/alternatives-to-vhdlverilog-for-hardware-design
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The document "xst user guide" from Xilinx shows the writing rules for your HDL to map on DSP slices http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/xst.pdf . These rules are likely to work for other vendors FPGA and since it's the H…
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The myhdl website has many examples in their examples section, but nothing that goes down to synthesis for a specific board. What kind of example would you like to get for the logi-pi ? I can add something with myhdl to the logi-project repository s…
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You may need to créateur the "work" directory at the dame level as the "ISE" directory. I will check if i can fix this on the gît but i am afraid that gît does nlt allow me to add an empty directory
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Do you know if dev2mem takes byte addressing or word (16-bits) addressing ? You could try to test with addresses 0xA000_0000 or 0x2800_0000. The address used to address the FPGA in the beagle mem-space is : 0x01000000 (in generic.h file of the log…
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Including SDB in skeleton would greatly improve the user experience. People working with skeleton usually struggle with setting the address peripheral right. You mention a Python based tool of you own, do you have anything to do with http://www.arma…
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Forking then requesting a pull seems like a good way to proceed. For the kernel patches this will be more difficult to distribute, but we can set a up a patches folder somewhere on the repository for advanced users.
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Great news ! Did you make it wotk using our wishbone wrapper as a base or did you write it from scratch ? One possibility could be to had your module to the repository or try to make the existing wrapper generic with th option for AAD instead of AD.
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The design for the LOGI-Pi are genrated through ISE and ISE supports Verilog, so no problem to use Verilog. Our examples were designed with VHDL but some users use Verilog. ISE support the synthesis of Verilog design that uses VHDL components and vi…