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beaglebone shared pins, dts overlay

mattvennmattvenn
in LOGI Troubleshooting Discussion
Hello again, I'm really getting stuck with not being able to find out basic stuff. Sorry if I've missed something obvious but I've been trying to do something simple all day and still getting nowhere.

I want to be able to communicate between the fpga and the bbb so I thought an easy way to get started would be to use the shared pins. For example fpga pin 105 is connected to bbb p8.13.

My fpga program just connects a button (also couldn't find this documented anywhere) to the led and pin 105. I can see the pin changing with my multimeter.

Previously on a bbb, I'd export the gpio with :

root@arm:~# echo 23 > /sys/class/gpio/export

then be able to inspect the value. Which doesn't work. Neither does the Adafruit python library.

So maybe the overlay isn't setup to handle these pins. I can't find in any of the source where the overlay is defined. I've searched /lib/firmware for the overlay (which seems to be loaded when I look at the slots:

 cat /sys/devices/bone_capemgr.9/slots
 0: 54:P---L BB-BONE-LOGIBONE,00R1,VALENTFX,BB-BONE-LOGIBONE

There is an "old" dts file in the repo ./old/beaglebone_old/logibone.dts but that file isn't in /lib/firmware.

So where is the overlay defined?
How can I access the GPIOs from userspace on the beaglebone?
Am I missing a whole trove of documentation somewhere?

Sorry for all the questions,
Matt

Comments

  • mjonesmjones
    Hi Matt,

    The easiest way to begin communicating between the FPGA/BBB is to use the logi-apps which are installed on the default logi-image.  The wishbone app is setup to for drivers and code on the BBB and FPGA using a python to wishbone gateway on the BBB.  http://valentfx.com/wiki/index.php?title=LOGI_-_Wishbone_-_Project

    Here is the latest *.dts file for the R1 logi-bone.  It can be modified to support adding other GPIO as needed.  

    Here are a couple of good tutorials on the overlays and implementing them.

    Hope this helps.



  • mattvennmattvenn
    edited August 2016
    what's the reasoning for not including the hdl files in the logi-apps directories? I've found them now but why not include them with the demos?

  • mattvennmattvenn
    edited August 2016
    I'm trying to  understand how the pwm example works. I can see in the vhl:
    https://github.com/fpga-logi/logi-projects/blob/master/logi-wishbone/hw/logibone/hdl/logibone_wishbone.vhd#L244

    which looks a bit like using a component with the port map (I'm a total beginner to this). I can't work out what's doing the work - are there other files I need to look at?

    Thanks for the help,
    Matt
  • jpiatjpiat
    To have a better understanding at what the PWM example do, you have a look at the example project for our architecture editor, Skeleton :

    http://valentfx.com/skeleton/arch_editor.html?board=logibone

    In this demo we have the Beaglebone external memory interface (GPMC bus) connected to a component that converts it to the wishbone bus (open source bus specification). A PWM component is then mapped on this bus, and the software can configure the different properties of the PWM by wirting to its registers. On the beaglebone, this external memory space is accessed through /dev/logibone and is wrapped in a library that provides easy to use read/write functions in C and Python. In the example, python code controls the PWM properties by using the provided library functions to write the PWM component registers:

    https://github.com/fpga-logi/logi-apps/blob/logibone/wishbone/test_wishbone.py

    On the device-tree aspect, the dts files are located in the official kernel sources and can be seen in the logibone patchset :

    https://github.com/RobertCNelson/bb-kernel/tree/am33x-v3.8/patches/logibone

  • mattvennmattvenn
    cheers, I think this is just what I was looking for. Right now I'm attaching a serial ADC to the fpga and doing conversions at ~2mhz. I'm hoping I'll be able to read that out using this interface.
    Matt
  • mattvennmattvenn
    github links on the wiki page for skeleton repo are broken, should be:

    https://github.com/fpga-logi/logi-hard.git

    not

    https://github.com/fpga-logi-dev/logi-hard.git
  • mattvennmattvenn
    edited August 2016
    I've successfully used the skeleton editor to create a simple structure with just a register. It synthesises (better than the one I made previous with no intercon component).

    From what I understand from this page on the wiki http://valentfx.com/wiki/index.php?title=LOGI_-_Wishbone_-_HW#Wishbone_addressing_in_the_HDL

    each wishbone slave peripheral gets its own base address. But I don't know where that will be. I can see this being used: Intercon_0_wbm_adc_reg_wbs_0.address but no idea where it's mapped to.

    Also there is lots of big blue writing on that page that says 'out of date'  - I don't want to waste my time on old docs!

    And how would I go about writing to the register on the FPGA? Can I use Intercon_0_wbm_adc_reg_wbs_0.address as a register?

    Does anyone have a simple example of reading and writing to a register via the wishbone interface?

    I've tried wishbone_write 0x0000 0x1234

    but wishbone_read 0x0000
    results in nothing.

    If I use the default test example, I can read and write to this address.
  • mattvennmattvenn
    Also, something to note is that if I synthesise the logi-apps wishbone example:

    and load that on the fpga, the wishbone_read & write  don't work.

    the provided bitstream in the logi-apps/wishbone on the beaglebone does work.
  • jpiatjpiat
    If you generate a project with a register in skeleton, the output and input of the register are not connected. If you want to be able to read the content you write, you need to connect the reg input to its output. I'll check why the wishbone app in logi-project does not work but it may be because the wrong constraint file is setup in the project.
  • mattvennmattvenn
    edited August 2016
    what I need to know is how to find what address the registers appear in.

    If I connect the in and out with a std_logic_vector I get this error when trying to synthesize:

    Line 55: Illegal identifier : adcreg_reg_out_0__adcreg_reg_in_0__0

    Are there any working examples of using a register? That would be a great starting point!
  • mattvennmattvenn
    regarding the non-working logibone-wishbone example, I get these warnings:

    WARNING:ProjectMgmt - File /home/mattvenn/work/fpga/logi-projects/logi-wishbone/hw/logibone/ise/ipcore_dir/clock_gen/example_design/clock_gen_exdes.ucf is missing.
    WARNING:ProjectMgmt - File /home/mattvenn/work/fpga/logi-projects/logi-wishbone/hw/logibone/ise/ipcore_dir/clock_gen/example_design/clock_gen_exdes.vhd is missing.
    WARNING:ProjectMgmt - File /home/mattvenn/work/fpga/logi-projects/logi-wishbone/hw/logibone/ise/ipcore_dir/clock_gen/example_design/clock_gen_exdes.ucf is missing.
    WARNING:ProjectMgmt - File /home/mattvenn/work/fpga/logi-projects/logi-wishbone/hw/logibone/ise/ipcore_dir/clock_gen/example_design/clock_gen_exdes.vhd is missing.


    If I try and add the logibone_ra3.ucf constraints file to the project, I get an error that tells me it's already added, though I can't see it in the file browser.
  • mattvennmattvenn
    I've finally managed to communicate via writing into a register that I can access with the wishbone read functions.
    I used the working pwm example (the preprogrammed example in the skeleton editor). I removed the pwm functionality and just used the configured registers.

    I'm still interested if anyone can help me with a simpler setup that just uses a single register.

    Matt
  • jpiatjpiat
    I have linked in an example file for skeleton with a single register that can be read/write. You can load it in skeleton through the browse at the top left of the window. Note that the register output is linked to its input. To get the memory address of the register, just click on the gte memory map button and a pop-pup will give your the assigned address for the register. You can then read/write to the register with the following python snippet : 
    import sys
    #path of the logi-hal on the host machine
    sys.path.append("/home/pi/logi-tools/python/")

    import logi_hal
     
    #address of the PWM component in the architecture
    REG_0=0X0000
    logi_hal.writeRegister(REG_0, 0,123) # 0 indicate that we write the first register in the register bank
    a = logi_hal.readRegister(REG_0, 0)
    print a


  • mattvennmattvenn
    THANKYOU!!!!
  • mattvennmattvenn
    Ah, where's the json configuration?
  • jpiatjpiat
    i had to change the name to txt, so you'll have to rename it to .json
    txt
    txt
    design.txt
    7K
  • mattvennmattvenn
    edited August 2016
    OK, I've tried the project created by the online editor and I get the same error as I did earlier.
    It doesn't look like an illegal name (starting with number of _) to me, so maybe it's to do with something else?
    Also last couple of errors about types not matching is confusing. I started changing the design.json to use std_logic instead of std_logic_vect but then thought it probably wouldn't work as it needs to be a 16bit wide bus.

    ERROR:HDLCompiler:488 - "/home/mattvenn/work/fpga/adc_reg/adc_reg.vhd" Line 55: Illegal identifier : REG_0_reg_out_0__REG_0_reg_in_0__0
    ERROR:HDLCompiler:488 - "/home/mattvenn/work/fpga/adc_reg/adc_reg.vhd" Line 131: Illegal identifier : REG_0_reg_out_0__REG_0_reg_in_0__0
    ERROR:HDLCompiler:488 - "/home/mattvenn/work/fpga/adc_reg/adc_reg.vhd" Line 133: Illegal identifier : REG_0_reg_out_0__REG_0_reg_in_0__0
    ERROR:HDLCompiler:488 - "/home/mattvenn/work/fpga/adc_reg/adc_reg.vhd" Line 55: Illegal identifier : REG_0_reg_out_0__REG_0_reg_in_0__0
    ERROR:HDLCompiler:488 - "/home/mattvenn/work/fpga/adc_reg/adc_reg.vhd" Line 131: Illegal identifier : REG_0_reg_out_0__REG_0_reg_in_0__0
    ERROR:HDLCompiler:488 - "/home/mattvenn/work/fpga/adc_reg/adc_reg.vhd" Line 133: Illegal identifier : REG_0_reg_out_0__REG_0_reg_in_0__0
    ERROR:HDLCompiler:1728 - "/home/mattvenn/work/fpga/adc_reg/adc_reg.vhd" Line 131: Type error near reg_0_reg_out_0__reg_0_reg_in_0__0 ; current type std_logic_vector; expected type std_ulogic
    ERROR:HDLCompiler:1728 - "/home/mattvenn/work/fpga/adc_reg/adc_reg.vhd" Line 133: Type error near reg_0_reg_out_0__reg_0_reg_in_0__0 ; current type std_logic_vector; expected type std_ulogic
    ERROR:HDLCompiler:854 - "/home/mattvenn/work/fpga/adc_reg/adc_reg.vhd" Line 32: Unit <structural> ignored due to previous errors.

  • mattvennmattvenn
    edited August 2016
    Also, regarding DTS stuff, I need to configure and use the PRUs.
    You said:

    On the device-tree aspect, the dts files are located in the official kernel sources and can be seen in the logibone patchset :

    https://github.com/RobertCNelson/bb-kernel/tree/am33x-v3.8/patches/logibone

    I don't really know what this means, it looks like it's compiled into the kernel? I can't remove the DTS or add a new one with the slots sys device.

    Here is the latest *.dts file for the R1 logi-bone.  It can be modified to support adding other GPIO as needed.  

    Looks out of date, the setup_device-tree_R1.sh

    file installs a dts file to /lib/firmware which doesn't exist in my /lib/firmware.

    To change the DTS what do I do, are there any instructions?
  • mattvennmattvenn
    Is this still true? I have to recompile the whole kernel to make a change to the dts?!

    http://valentfx.com/wiki/index.php?title=Develop_new_driver_for_LOGI-Bone

    http://valentfx.com/vanilla/post/quote/71/Comment_244

    Is there a reason I can't use a runtime inserted dts?
  • jpiatjpiat
    Hi,

    good news, with your latest remarks, i built a new image based on 4.4 kernel that enables dynamic loading of overlays. The new image is not on the server yet, but pm me and i'll send a link for you to download and test. The image contains the device-tree overlay that you can modify and load at run-time. (its a 16.04 Ubuntu image).
  • k1rak1ra
    Is the 16.04 Ubuntu image now available for download anywhere?

    Thanks

    k1ra
  • danielvilasdanielvilas
    edited May 2017
    Hi,

    I am also interested on the ubuntu image, but I have managed to use the  beagle debian oficial image(Debian
    8.7
    2017-03-19
    4GB SD
    LXQT    ) and doing this:
    <<
    cd /opt/scripts/tools/
    git pull
    sudo ./update_kernel.sh
    sudo reboot


    sudo apt-get update
    sudo apt-get install device-tree-compiler 
    sudo reboot

    cd logi-kernel/beaglebone-black/logibone_r1/
    dtc -O dtb -o BB-BONE-LOGIBONE-00R1.dtbo -b 0 -@ BB-BONE-LOGIBONE-00R1.dts
    sudo cp BB-BONE-LOGIBONE-00R1.dtbo /lib/firmware
    sudo update-initramfs -uk `uname -r`
    sudo reboot

    cd
    cd logi-tools/unified_loader/
    nano logi_loader.h 
      change spidev to dev/spidev1.0
    cd ..
    sudo ./install_logibone.sh
    sudo reboot

    cd
    logi_loader logi-apps/blink_led_app/logibone_r1_blink.bit 

    sudo apt-get auto remove
    >>
    Thanks
  • pentesgeorgepentesgeorge
    Hello,
    can i have also the new image?
    I want to use PRU with logibone. I have kernel 3.8.13. I created a new .dts file  but i get a prussdrv_open() failed.

    Thank you,
    George
  • angilbertoangilberto
    Hi,
    by any chance, is the image "based on 4.4 kernel that enables dynamic loading of overlays" mentioned by JPIAT available somewhere for download?

    Thank you,
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