claudiug

• SATA , SDRAM code

  claudiug

  July 2014
  Hi all,
  
  although probably very obvious to people familiar with SATA, I'd like to mention that a "normal" SATA cable will connect two logibones as
  D1_P<->D1_P
  D1_N<->D1_N
  D2_P<->D2_P
  D2_N<->D2_N
  
  This means that clk input pins go together on both logibones. I was planning on fwd a clock to a DCM_SP from one logibone to the other and then fwd back to the original logibone. For this you'd need a "crossover" SATA cable.
  
  With proper connection (i.e, D2_P/N as input on one logibone and as output on the other) one can get a DCM_SP to lock on the clock from the other logibone. I've used LVDS_33.
  
  -C
  

  

• Getting started with Xilinx tools

  claudiug

  July 2014
  You need ISE 14.7 Webpack:
  http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html