claudiug

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• Hi all, although probably very obvious to people familiar with SATA, I'd like to mention that a "normal" SATA cable will connect two logibones as D1_P<->D1_P D1_N<->D1_N D2_P<->D2_P D2_N<->D2_N This means that clk input pin…

  in SATA , SDRAM code Comment by claudiug July 2014
• Hi, It never worked for me in Firefox. With the newer IE11, it seems that it has the same behavior as Firefox, it prompts you to download the file (rather than installing the Akamai downloader). I would do the following. Start the download in IE. …

  in Getting started with Xilinx tools Comment by claudiug July 2014
• You need ISE 14.7 Webpack: http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html

  in Getting started with Xilinx tools Comment by claudiug July 2014
• Mike, I now have another question. How to write the FLASH? Is it better to use an FPGA design that bitbangs via IO_L1P_CCLK2/IO_L3N_MOSI... and write the bitfile to FLASH through the gpmc, or is it easier to just hook up FLSH_MOSI to a BBB GPIO/CFG…

  in SATA , SDRAM code Comment by claudiug June 2014