Iceage
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In addition, I am currently researching a 3.0v low dropout low noise regulator for the analog supply (AVDD) for the design. Here is what I am proposing http://uk.farnell.com/analog-devices/adp150aujz-3-0-r7/150ma-ultra-low-noise-ldo-3-0/dp/23…
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@mjones thanks for this and to just push the envelope, I have just done it from my iPad! It'll be great to hear your thoughts, my design will feed the ADC from a logarithmic detector. Cheers, Andy.
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Hi Guys, Apologies but I got distracted with the front-end design that I want to interface the ADC to. Anyways I have attached what I have so far but must admit I have now moved away from gEDA Schematic and started using Upverter instead. You …
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Hi all, @mjones That ADC that you have found is a very interesting component. I have taken a good look and it looks like it is a parallel LVDS device We don't have enough IO on the Logi for one of those, do feel free to correct me though. NXP are…
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@meg768 You could follow this handy guide here I have found this article about Capes and eeproms invaluable recently. Cheers, Andy.
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Hi Guys, LVDS is too expensive for the project that I have in mind. I have been doing a little research this week and apologies for the late reply but do you think that we could use the Arduino header for this purpose using a parallel ADC such as th…
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Jonathan, Thank you for your guide to updating my image, I am now on Bone63 release and all is working ok with my IO. Regards, Andy.