chrisoutwright
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- chrisoutwright
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Mhh, in the file rgb_32_32_matrix_ctrl.vhd i found following code I can't follow: signal pixel_write_addr_line0, pixel_write_addr_line16 : std_logic_vector((nbit(32*32*nb_panels))-1 downto 0); signal pixel_write_addr : std_logic_vector((nbit(32*32…
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I hoped that I could adapt the coding for the bigger size panel, with the support here. I will have to commit the request to my local marketspace, to solve with remuneration. Interest is sparse here for help. Seems a better way sadly at the moment.
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@jpiat. I have come along a bit by playing around with one 32x32 panel, seems to work fine. Sadly using additional panels, even when modifying "nb_panels =>2" is getting me nowhere. Also changing the the buffer function (seems logical with nb_p…
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I managed to drive a 32x32 RGB Panel with the tips above. Looking at the vhd files of "logibone_mat.xise" is it possible to drive a 32x64 Panel with minor adjustments? Setting nb_panels : positive := 4 for two 32x64, does not work nor does nb_p…
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Hello together, I am new to FPGA and beaglebone. I managed to drive a 32x32 RGB Panel with the tips above. Looking at the vhd files of "logibone_mat.xise" is it possible to drive a 32x64 Panel with minor adjustments? Also the python script seems to…