SquareOne
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hi, if your MT9V034 board is ready i am interested in that . how about the drivers have you implemented drivers for that and integrated in to logibone
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i have something to say on this topic . I am vision developer and with the current board everything is ok which i really would like to happen is following 1) Direct programming with FPGA is still difficult . with different sensor integration and …
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So now these logi-machine-vision FIFO connected to SDRAM ? Can we use full frame 640x480 or any other sensor size image to buffer it and the nuse that FIFO in logi-bone . Above implementation is working .
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Hi, What is the process time on FPGA for image processing pipeline . can it be measured. so in this project are you using full frame resolution.
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yes i would be interested in your LVDS camera design .
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Hi, Any progress on the SDRAM interfacing front . we are eagerly waiting for this . We are planning smart camera plateform based on this . like www.microscan.com . We are preparing software based on .net and will run it using .net mono plateform.…
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i found this link has designed http://hamsterworks.co.nz/mediawiki/index.php/Simple_SDRAM_Controller SDRAM controller for Logi Bone . is this working can we use it .
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could you define block diagram for SDRAM from code that i sent you. i can try to design SDRAM code from my friends.
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Have u got chance to review fifo vhdl code i sent u. It is for altera but design should be same for xilinx .
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ok i will E-mail the complete code to you
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Regarding FIFO with on board SDRAM . i have one USB3 Kit from Haunor which has Cyclon III and has Two SD ram. htey have written Hardware RAM access controller for FIFO write to FX3 and read FIF from FX3 32 bit . if you want the VHDL code for that i…
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Any progress on this matter . Regards,
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for Image processing we need raw image . as by compressing it will be loss of some information. as Raw FIFO buffer of image would be usefull to do image processing in OpenCV. Along with that how about triggering camera for single frame grabbing .…