Hi Jonathan,
That was very nice project. i was wondering that for the Image processing algorithms that were implemented on FPGA . can we gesign reconfigurable type architecture like what LabView FPGA provide . you dynamically Switch module in pipeline.
i.e Image-->Filters(Sobel,Amp,Prevwitt)--> ROI Cropping -->(User defined algorithm ) --> FIFO-->BeagleBone
so in Beagle bone C program or by some Phyton script we will just swithc on /of off as per your selection theses algorithm.
Comments
What is the process time on FPGA for image processing pipeline . can it be measured. so in this project are you using full frame resolution.
the processing time is the image acquisition time, as no more than two lines of the image are stored for processing. So as soon as the last pixel of the image is received, the line is detected. The current version of the project is only using QVGA as setup in the repository, but switching to VGA is only a matter of sensor configuration, and some of the architecture parameters must be changed.
Changing the processing pipeline is definitely possible, and i even have a project setup for this (logi-machine-vision), that source image from a fifo, then a set of values configures the sequence of processing (there is gauss, sobel, erode, dilate, threshold operators that can be linked). The same could be done with the camera in the pipeline.
Regards,
Jonathan Piat
Above implementation is working .