LOGI - Wishbone - Project
The wishbone bus is a open source parallel bus generally used internally in FPGAs or ASICs to interconnect a master or multi-master with many slave peripherals. The wishbone bus was chosen as an interconnect for the LOGI FPGAs as there are a multitude of available cores available that can be directly and easily implemented within the all the majority of the LOGI project architectures. Open cores and many other online resources provide source for peripheral implementation that are compatible with wishbone.
The LOGI-Team provides wishbone wrappers that make it easy to start talking from your BeagleBone or Raspberry Pi to the LOGI FPGAs. There are SPI and GPMC wishbone wrappers that allow the Pi/Bone to directly communicate with the FPGA without any need to use special protocols. Just install the logi-tools on your host and start talking.
Below is block diagram that show the top level interconnect of the Raspberry Pi SPI port to the wishbone master (Master_0) inside of the LOGI FPGA. You can see that the user can then connect any number of wishbone compatible slave peripherals to the wishbone master that then can communitcate directly with the Raspberry Pi.
Currently Available LOGI wishbone peripherals
- Servo Controller
- PWM Controller
- PID Controller
- NES Controller
- SSEG display Controller
- MCP3002 ADC Controller
- Heart Beat Controller
- GPIO Controller
- Memory Controller
- Watchdog Controller
With many more to come......
The LOGI Skeleton editor is a great example of the felxibility of the wishbone architechture. The user can dynamically connect any number of components in a Web Based GUI and a the wishbone architecture and peripheral RTL is automatically generated.
Functional Overview of the Wishbone Demo - LOGI App
The wishbone Demo is designed to showcase how to interface with the wishbone peripherals on the FPGA from the RPi or BBB hosts. The LOGI-Team has created drivers that make it easy to directly comunicate using C or Python API function calls. This demo will step you through how to use either C or python to begin talking wishbone. The FPGA HDL project has setup the internal registers for reading and writing to including static registers, R/W registers and PWM peripheral registers driving the LEDs
Running the Wishbone Demo LOGI-App - Step by Step Guide
getting the logi-apps
The demo resides within the logi-apps. So the easiest way to run the demo is the download and run the demo using the instructions found on the logi-apps wiki page. In short you can download all of the logi-apps by running "git clone -b logipi https://github.com/fpga-logi/logi-apps.git " . You can then navigate to the Wishbone demo directory and run "sudo ./make_demo" to load the bit file and display basic instructions for the edu demo.
Step by Step
Experimenting with the Python Wishbone API calls
1) Navigate to the installed logi-apps/wishbone directory and run "sudo ./make_demo.sh". Note the the make_demo script calls the logi_loader which loads the bistream into the FPGA.
The shell script will auto launch a python script. The Python script imports the logi-tools wishbone API library and is able to begin communicating with the FPGA. Python reads a couple of pre-defined register within the FPGA and outputs the register data. It then sets up the PWM registers that are driving LED1 and begins a loop where it calculate the sine value of and loads the duty cycle register within the FPGA. The results are a visible sinusoid on LED. Note tha the sinusoid data is no gamma correct, so it does not appear to have a linear reponse, though you can see it being updated.
2) type control-C to exit the python script.
You can open the python script file "nano test_wishbone.py" and see how basic it is to read and write to the wishbone bus. You can modify the time "t" value to increase or decrease the loop delay and add some code to make the LED dance to your liking. You can re-run the script again by re-running the make_demo.sh or manually running the python script "sudo python2 test_wishbone.py".
3) You can also use the C wishbone API calls to communite with the wishbone bus. The C functions are in the "sw" directory of the wishbone app. Navigate to the "sw" directory "cd sw". View the available files "ls". Note that there are built executables "read_wishbone" and "write_wishbone" along with the C source code for communicating with wishbone.
Experimenting with the C Wishbone API calls
The FPGA HDL project has setup the following registers including some static registers, R/W registers and PWM peripheral registers driving the LEDs. Below is the register address map to read and write to the registers. Below there are
address | name | note |
0x0000 register_0 read :0xDEAD
0x0001 register_1 read : 0xBEEF
0x0002 register_3 read/write register
0x0003 register_4 write pmod2/read pmod1 and switches
0x0008 pwm_divider system_clock divider for pwm
0x0009 pwm_period pwm signal period
0x000A pwm0_high high time for pwm0 (unconnected)
0x000B pwm1_high high time for pwm1 connected to LED0
0x000C pwm2_hight high time for pwm2 connected to LED1READ REGISTER ON THE FPGA
Reading the static registers:
1) Read register 0x0000 on the FPGA
sudo ./read_wishbone 0x0000
should return 0xdead
2) Read register 0x0001 on the FPGA
sudo ./read_wishbone 0x0001
should return 0xbeef
WRITE AND READ AN UNINITIALIZED REGISTER ON THE FPGA
1) read the uninitialized register_3 (0x0002)
sudo ./read_wishbone 0x0002
should return: 0x0
2) write a value of 0x1234 to register_3
sudo ./write_wishbone 0x0002 0x1234
should output: Writing 0x1234 @ 0x2
3) read back the contents stored in register_3
sudo ./read_wishbone 0x0002
should return: 0x1234
SETUP LED PWM REGISTER TO CONTROL THE INTENSITY OF THE LEDS
1) Load the clock divider register with 0x0008
sudo ./write_wishbone 0x0008 0x0004
should return: Writing 0x4 @ 0x8
2) Load the period register with 0x0800
sudo ./write_wishbone 0x0009 0x0800
should return: Writing 0x800 @ 0x09
3) Load the LED1 register with the duty cycle value
sudo ./write_wishbone 0x000B 0x0080
should return: Writing 0x80 @ 0x0B
you should see LED1 light up with the brightness relative to pwm_period/pwm_duty(high time)
4) Load the LED0 register with the duty cycle value
sudo ./write_wishbone 0x000C 0x0080
should return: Writing 0x80 @ 0x0C
you should see LED0 light up with the brightness relative to pwm_period/pwm_duty(high time)
5) Experiment with setting the brightness of the LEDS by writing the the pwm_high registers
So, you are now a wishbone communicating guru! You will note that we are using this wishbone framework in the majority of our projects. It lends itself to great flexibiltiy, performance and extendabiltiy. We have provided all of the source code for the HDL, SW and have an ever growing range of drop-in peripherals that we make available. See the list of available LOGI wishbone peripherals. Additionally wishbone is widely used in the industry as the "open source" standard for FPGA and ASIC communication. Opencores.com is a great resource and repository for many open source "cores", many of which are wishbone compatible.
Where To Go From Here
Opencores.com for a listing of 3rd party open source HDL Cores. Many of which are wishbone compliant and directly comptible with the LOGI wishbone architecture.