mattvenn
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Is this still true? I have to recompile the whole kernel to make a change to the dts?! http://valentfx.com/wiki/index.php?title=Develop_new_driver_for_LOGI-Bone http://valentfx.com/vanilla/post/quote/71/Comment_244 Is there a reason I can't use a…
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Also, regarding DTS stuff, I need to configure and use the PRUs. You said: On the device-tree aspect, the dts files are located in the official kernel sources and can be seen in the logibone patchset : https://github.com/RobertCNelson/bb-kernel/tr…
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OK, I've tried the project created by the online editor and I get the same error as I did earlier. It doesn't look like an illegal name (starting with number of _) to me, so maybe it's to do with something else? Also last couple of errors about typ…
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Ah, where's the json configuration?
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THANKYOU!!!!
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I've finally managed to communicate via writing into a register that I can access with the wishbone read functions. I used the working pwm example (the preprogrammed example in the skeleton editor). I removed the pwm functionality and just used the …
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regarding the non-working logibone-wishbone example, I get these warnings: WARNING:ProjectMgmt - File /home/mattvenn/work/fpga/logi-projects/logi-wishbone/hw/logibone/ise/ipcore_dir/clock_gen/example_design/clock_gen_exdes.ucf is missing. WARNING:P…
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what I need to know is how to find what address the registers appear in. If I connect the in and out with a std_logic_vector I get this error when trying to synthesize: Line 55: Illegal identifier : adcreg_reg_out_0__adcreg_reg_in_0__0 Are there …
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Also, something to note is that if I synthesise the logi-apps wishbone example:https://github.com/fpga-logi/logi-projects/tree/master/logi-wishbone/hw/logibone and load that on the fpga, the wishbone_read & write don't work. the provid…
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I've successfully used the skeleton editor to create a simple structure with just a register. It synthesises (better than the one I made previous with no intercon component). From what I understand from this page on the wiki http://valentfx.com/wik…
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github links on the wiki page for skeleton repo are broken, should be: https://github.com/fpga-logi/logi-hard.git not https://github.com/fpga-logi-dev/logi-hard.git
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cheers, I think this is just what I was looking for. Right now I'm attaching a serial ADC to the fpga and doing conversions at ~2mhz. I'm hoping I'll be able to read that out using this interface. Matt
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ah ok. my only other experiences with the bbb have been loading the dts after boot. That also explains why I couldn't find the overlay in the usual place.
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I'm trying to understand how the pwm example works. I can see in the vhl: https://github.com/fpga-logi/logi-projects/blob/master/logi-wishbone/hw/logibone/hdl/logibone_wishbone.vhd#L244 which looks a bit like using a component with the port map (I…
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what's the reasoning for not including the hdl files in the logi-apps directories? I've found them now but why not include them with the demos?
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It seems the eeprom was written, it was the 2 i2c write commands that failed. I can read the eeprom out with sudo cat /sys/bus/i2c/devices/1-0054/eeprom | hexdump -C I don't know what the i2c commands are meant to do. I found the slots: cat /sys…