jpiat
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The done pins is only hi-z hence the 1.8v of the led. ISE can be configured to write a logic one (3.3v) to the done pin at the end of loading. I have disabled the done pin check in the code until we provide you the relevant information on how to con…
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For the LOGI-Bone there are minor differences on the way the i2C GPIO expander is wired (the expander controls some of the programming interface pins) to allow a easier use of the configuration flash of the FPGA. For the LOGI-Pi there is one major …
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The flag won't change anything in your case as the LOGI-PI-2 has an I2C expander to manage the programming port while the v1 was doing it in bit-bang (thus the mappin gof the GPIO different on PI2 and PI1). On you board even if the message done not…
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For those who received their LOGI-PI2, the loader is available on the github. To install the new loader, clone (or pull) the logi-tools repository on your raspberry-pi, go to the unified loader folder and do : make logipi_loader sudo make install …
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The loader is ready and works, i just need to clean the code a bit to allow it to auto-detect between a rev2 logi-pi and a rev1 logi-pi.
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Congrats ! You got it so fast that the software support (the loader) is not totaly public yet ... Let me know when you start working with it so i can provide more direct support and get direct feedbacks. Regards, Jonathan Piat
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We encountered the same issue several time and it sometime appears that even using the "Project -> cleanup project files" would not change anything ... only rebooting ISE would work (its very rare though). In Project there is event a "Force hier…
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Hi, to get auto loading of the device-tree overlay for a given beaglebone cape, the device-tree must reside in the kernel itself and not in lib/firmware. This is why the device-tree configuration does not appear in lib/firmware. To change the devei…
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Hi, i have been looking at those display (the SPI based ones like adafruit HAT); but never used them with the LOGI-Pi. The main issue is that the display uses the only SPI port and its two slave select pins pllus some GPIO. The SPI port is used for…
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We don't have a quick guide on this, but it will require a Xilinx JTAG and to solder the JTAG header on the board (the boards comes with the JTAG connector not soldered (6 pin connector close to the ethernet jack on logi-bone and above the ethernet …
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You are right that the RPI_GPIO pnis are the most likely to create the bug. What i observed with raspberry-pi is that shuting it down is just performed in software (compared to beaglebone black that shutdown its own voltage regulator and really shut…
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Never encountered this bug ... Can you link in the top-level file that you are using ?
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Hi, never tried doing this. Do you know if the PRU can directly access the L3 memory system ? If the GPMC is configured by Linux, then it should be fairly easy to access the GPMC as its memory mapped.
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Great ! Concerning the GPMC timings, i have set them to be a bit conservative but stable. The data should be ready after 80ns as you noticed but there is an unknown phase relationship between the gpmc clock and the system clock in reality. I'am wo…
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The problem is not only about crossing clock domains. The SDRAM access is inherently slow because of the initial adressing latency that is 11 clock cycles for four words. The burst mode of the SDRAM (back-to-back reads/writes) allow to achieve a bet…
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Hi, this is a very good idea and it will clearly help with acessing the SDRAM from the Cortex. The option your propose would work, you would just need to cut the connector pin that connects BE1N to the BBB and solder BE1N and GPMC_WAIT together on…
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HI, 1) you cannot load two bitfiles into one FPGA. The bit file configure all the logi resources of the FPGA at once, and thus it is not possible to load part of the FPGA with one design and another part with another design. 2) There is no problem…
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Hi, i just corrected a bug in teh loader coe that was updated for PI2, can you do a gill pull on logi-tools ? For the PI2, there are multiple things to do before eveyrthing works : 1) to a clean in stall of latest logi-tools 2) go in the logi-tool…
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Look at what the PMOD cam really look like : http://www.digilentchina.com/product-more.asp?ClassId=21&Unid=807 They are using two PMOD as we do.
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Its unlikely that this cam uses a single PMOD as its has 16pins (base on picture) and a PMOD only has 12 IO (including 4 pins for VCC/GND, hence only 8 pins for IO). On the LOGI-Bone doing stereo on the two PMODS is unlikely, we are working on a so…
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Can you check that you have logibone_mem in /dev ? It seems that you have the correct module loaded, and if you can load the bitfile in the FPGA, its good news. I'am a bit surprised that you still ahve the line 0: 54:P---- BB-BONE-LOGIBONE,00R1,VAL…
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We don't have the ports to connect a CSI-2 camera (LVDS bus with one line for differential clock and two lines for differential data), but we have the SATA port that is capable of doing communication with some of the camera available. The goal is no…
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Sure, this is something we should add to the wiki. If you want to understand the signals coming out of the camera and how they are interfaced in the FPGA you can have a look at : http://www.element14.com/community/groups/fpga-group/blog/2014/12/17/…
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The camera module of the raspberry pi uses LVDS signals between the camera sensor and the Rpi ( for pixels), allowing less conductors to be used and allowing to maintain a better signal integrity on "long" flat-cables. The logi-camera module use a…
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I have some ov9655 module that i bought from ebay with a breakout board that convert the FCC cable into headers at the same format the ov7670. same as : http://www.ebay.fr/itm/OV9655-Camera-Board-Module-CMOS-Camera-Module-1-3MP-Camera-Chip-Develop…
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Hi, you are right in saying that this particular sensor is available on a FCC cable and could be directly connected to the FPGA pins but we want to keep this camera as a module to the general purpose platform that is the LOGI-Pi/Bone. There are als…
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You are right in saying that a GPU as more horsepower (and easier ti use development tools) than a FPGA, but they have lower power/performance ratio than what a FPGA can achieve. Comparison of FPGA vs GPU are often made, but they make little sense …
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Maybe you should try this image : http://valentfx.com/doc/logi-image/logibone/logi_ubuntu-14.04-console-armhf-2014-08-13.img.zip which is more up to date with current logi software (see http://valentfx.com/wiki/index.php?title=Logi-Bone_Quick_Start…
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You can sure get a faster connection by wiring a parallel bus between the UDOO and the LOGI-Board, but this parallel bus will have to be managed in software (bit-banged bus) if your processor does not have an external memory bus (i haven't digg into…
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Hi, If you are running the logi imatge we provide and don't update the kernel you should be fine. I fyou download latest Debian/Ubuntu distro from beagleboard.org, things won't work as the integration of device tree into the BBB kernel is now a bit…