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• Sorry it took so long, but I had to rework the module completely as I could not get it pass the stress tests I wrote. Now it is finally working and I have sent the pull-request on Github. Feedback/suggestions are welcome. https://github.com/fpga-lo…

  in Logibone GPMC(AAD) to WBM interface Comment by jcdevel January 2016
• I am having some trouble implementing the write operation in burst mode. I think it is a timing issue but it is hard to say because I do not have a logic analyzer or any equipment to check the signals in the GPMC bus. I am going to double check the …

  in Logibone GPMC(AAD) to WBM interface Comment by jcdevel December 2015
• I am running some more tests before pushing externally, just to make sure that everything is working as expected. I should have something ready in a couple of days (hopefully). I will let you know. Thanks, JC

  in Logibone GPMC(AAD) to WBM interface Comment by jcdevel December 2015
• Hello Jonathan, I used the wishbone wrapper as a reference, but the implementation is quite different, so I do not think we can merge both modules in a generic wrapper. Good news is that the interface is compatible with the standard wishbone wrappe…

  in Logibone GPMC(AAD) to WBM interface Comment by jcdevel December 2015
• Hello Jonathan, I have followed your suggestion and I have instantiated a small cache (4KB for testing purposes) using block memory. I have not implemented the flushing mechanism yet, just accessing this small memory. It works fine except for I had…

  in How to generate a GPMC_WAIT signal for SDRAM access? Comment by jcdevel March 2015
• Hi Jonathan, I have tried different solutions, none of them successful so far. As you correctly pointed out on Github, crossing clock domains is a slow operation if we want to avoid metastability (specially on the way out, because the clock frequen…

  in How to generate a GPMC_WAIT signal for SDRAM access? Comment by jcdevel February 2015