At Present Image frame capture in FPGA is supported through FIFO SD RAM buffer . For Smart Camera image processing SD RAM buffered image capture will be helpfull so that one does not loose Frame if triggered by external source.
You are totally fright and this is something i have been working on (with no good results) so far. I'll try to explain the complexity of such task. The SDRAM has only one port, meaning that you cannot write (from the camera) and read (from the processor) at the same time. This means that you need to create some rules indicating priority and how to grant access to the reader or the writer. More-over the SDRAM access is efficient only when doing burst access. Burst access means that you access multiple consecutive data in memory in one operation. If not using burst access the bandwidth is below 25MB/s and while doing burst you can go as high as 200MB/s (read or write). So to handle a capture buffer there are two solutions : -come up with an application specific component. In this cas the camera could write to a buffer in the FPGA Block RAM and this buffer would sometime be flushed to the SDRAM. On the wishbone size, there would be a block ram that is refreshed with limited content from the SDRAM and then be accessed by the processor. This kind of technique is an application specific cache management (the block ram can be called cache) - Create a component that allows to share the SDRAM between multiple components (multi-port memory controller). This would require to determine a generic cache handling strategy that provide an optimized bandwidth for most cases.
While the first option should be fairly easy, it lacks genericity and thus cannot be used for other application. Moreover it means that the SDRAM is fully reserved for the buffer and cannot be used by other components in the architecture. For the moment i have tried to implement a generic multi-port memory controller, but its not an easy task. If someone want to help with this, i'd be grateful !
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-come up with an application specific component. In this cas the camera could write to a buffer in the FPGA Block RAM and this buffer would sometime be flushed to the SDRAM. On the wishbone size, there would be a block ram that is refreshed with limited content from the SDRAM and then be accessed by the processor. This kind of technique is an application specific cache management (the block ram can be called cache)
- Create a component that allows to share the SDRAM between multiple components (multi-port memory controller). This would require to determine a generic cache handling strategy that provide an optimized bandwidth for most cases.
While the first option should be fairly easy, it lacks genericity and thus cannot be used for other application. Moreover it means that the SDRAM is fully reserved for the buffer and cannot be used by other components in the architecture. For the moment i have tried to implement a generic multi-port memory controller, but its not an easy task. If someone want to help with this, i'd be grateful !
Best regards,
Jonathan Piat