SDRAM-FIFO-Test Project

Dear group members,

Currently, I am working on BBB and Logi-bone and learning how these two boards are working together. As I am familiar with FPGA designing but not so much with Linux. 

Initially, I have tested some logi-apps project and understand the communication of GPMC interface (not completely). My project is to make 1284 parallel port design in FPGA which recieves the data (min speed of 8MByte/s) from BB black and save into SDRAM on logi-bone. I have found one project relating this SDRAM_FIFO test but there is only HW section (VHDL files) but not the SW part. Also, if anyone wants to make a new cape like logi-bone then what should be necessary for configuration, Device tree overlay etc.

Have anyone on this platform who performed this task with software (sending/receiving data from BB Black through GPMC). 


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