Logi-Pi Quick Start VHDL library selection

The Logi-Pi blink project shown on the quick start WIKI page uses the IEEE.STD_LOGIC_UNSIGNED library.  This library and the IEEE.STD_LOGIC_SIGNED, and IEEE.STD_LOGIC_ARITH were created by Synopsys to fill deficiencies in the standard VHDL.  Unfortunately Cadence and Mentor created their own versions of these libraries creating significant issues with portability between simulators and syntheses. Though this library defines itself as a IEEE library, the real IEEE libraries are the IEEE.NUMERIC_STD and IEEE.NUMERIC_BIT. The numeric libraries have the blessing of the IEEE standardization body and are preferred over the Synopsys libraries.  The code itself has the following advice in a comment, but is not followed:
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;


I recommend the following change:
----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    23:46:35 07/06/2014 
-- Design Name: 
-- Module Name:    logi_blink - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity logi_blink is
    Port ( OSC_FPGA : in  STD_LOGIC;
           LED : out  STD_LOGIC_VECTOR (1 downto 0));
end logi_blink;

architecture RTL of logi_blink is
SIGNAL counter_output : unsigned(31 DOWNTO 0);
begin

process(OSC_FPGA)
begin
IF(OSC_FPGA'event AND OSC_FPGA = '1') THEN
counter_output <= counter_output + 1;
END IF;
END PROCESS;

LED(0) <= counter_output(24);
LED(1) <= counter_output(23);

end RTL;


I also renamed the architecture to TRL since this design is meant to run in hardware.


Pat

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Comments

  • Hi,

    thanks for the hint. I never used std_logic_arith because i knew it was deprecated but never knew that they were also deprecated. Can you fork our repository do the modification and then apply for a pull request so every user can benefit from you future changes ?

    Thanks for posting your modification to the forum so all our user can benefit from your experience.

    Regards,

    Jonathan Piat
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