SATA , SDRAM code

mjones

@claudiug has asked some good questions through email that I thought would be useful for other so I am pushing them here to the forums.  

Claudiug:

 Is there any way to use the SDRAM on board without a MIG? According to this

http://www.xilinx.com/publications/prod_mktg/Spartan6_Product_Table.pdf

the TQG144 package does not have MIG support. I need to read the Micron specs, but do you have any hints on implementing something successfully? 

For SATA based inter-fpga communication did you try anything?

Mike: 

We currently have an SDRAM driver.  It has been tested up to 166Mhz.  This should get you started.  We would like make it as easy to use as possible.  Maybe it would be a good idea to crate an SRAM wrapper or similar?

https://github.com/fpga-logi/logi-projects/tree/master/logi-sdram-test

Note that the LX9 is not capable of SATA communication  The SATA connector was used to employ maximum bandwidth LVDS communication offboard.  We hope to design some module at some point.

Claudiu:

I know it is not the SATA protocol, I'd like to use the SATA connector for LOGIBONE2LOGIBONE connection.

Mike:

Nice.  Hopefully you can share your code when you do the bone2bone!  I need to do the same.  I want to setup a test to measure the max bandwidth test using 2 fpgas with the built in test code generators and decoders.  This would consist of using PRBS pattern on 1 fpga  and use a 2nd logiboard to implement a PRBS checker.  Would be happy to hear what you come up with.

claudiug

Mike,

I now have another question. How to write the FLASH? Is it better to use an FPGA design that bitbangs via IO_L1P_CCLK2/IO_L3N_MOSI... and write the bitfile to FLASH through the gpmc, or is it easier to just hook up FLSH_MOSI to a BBB GPIO/CFG_CCLK through U3?

I'll definitely share any code I have related to LOGI2LOGI. I'm still going through understanding the connection paths to the board/within the board before I start implementing something.

Thank you for all the help,
Claudiu

jpiat

Hi claudius,

we haven't written the flash loader code for now because we found the loading from the host system very convenient. There is two ways, the flash could be loaded from the beagle :
1) Load a flash loading design in the FPGA and then use the GPMC to send configuration to the FPGA, that is then writtent to flash
2)Use a design t ocontrol CS of flash and then directly write design to flash using the beaglebone SPI.

The first technique could be much easier to implement and we will implement a flash loaded when we find the time.

claudiug

Hi all,

although probably very obvious to people familiar with SATA, I'd like to mention that a "normal" SATA cable will connect two logibones as
D1_P<->D1_P
D1_N<->D1_N
D2_P<->D2_P
D2_N<->D2_N

This means that clk input pins go together on both logibones. I was planning on fwd a clock to a DCM_SP from one logibone to the other and then fwd back to the original logibone. For this you'd need a "crossover" SATA cable.

With proper connection (i.e, D2_P/N as input on one logibone and as output on the other) one can get a DCM_SP to lock on the clock from the other logibone. I've used LVDS_33.

-C