Constraint file to use when connecting a VGA monitor to the Logi-bone

socjcare

I am fairly new to FPGA programming and I just got a Logi-bone ( Rev 1.5.1) last week. I want to connect a VGA monitor to it and run the examples in Chapter 12 of the Pong Chu book.

.\ logi-projects-master\book-example-code\pong-chu-logi-edu-examples-vhdl\ch12\ch12_02_vga_sync_test,

but I am not sure how to modify the constraint file so that it will work with the Beaglebone Black. I don't want to damage my Logi-bone if I do something incorrectly.

I see the logipi_r1_0_edu.ucf in  folder above, which as you can see is for the Pi.

### VGA outputs
###========================================================
NET "red<0>"  LOC = P116     | SLEW=FAST        ;    //P3_10
NET "red<1>"  LOC = P88     | SLEW=FAST        ;    //P1_7
NET "red<2>"  LOC = P5     | SLEW=FAST        ;    //P1_1

NET "green<0>"  LOC = P123 | SLEW=FAST        ;    //P3_4   
NET "green<1>"  LOC = P92 | SLEW=FAST        ;    //P1_8
NET "green<2>"  LOC = P2     | SLEW=FAST        ;    //P1_2

NET "blue<0>"  LOC = P124 | SLEW=FAST        ;    //P3_3
NET "blue<1>"  LOC = P93     | SLEW=FAST        ;    //P1_9
NET "blue<2>"  LOC = P1     | SLEW=FAST        ;    //P1_3

NET "vsync"   LOC = P94     | SLEW=FAST        ;    //P1_10
NET "hsync"   LOC = P16      | SLEW=FAST        ;    //P1_4   

I was thinking of using the PMOD1 and PMOD 2 pins , so I"ll have to change the LOC values to the correct ones in PMOD1 pins. Is this all that is needed?

I would also appreciate if someone can forward a link describing the User constraints. I downloaded one from Xilinx (UG625) but it wasn't clear to me. Is there any simplified guide to configuring the constraints.

Thanks

mjones

Hi @socjcare  Are you using the LOGI EDU board?  

Yes all that you will need to do is to change LOC values for the differing pins on the LBone pmod pins that are connected to your VGA signals.

Here is possibly more user friendly guide to constraints on xilinx parts:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgd.pdf

In short the constraints are passing in configurable attributes from the UCF file to the synthesis tools which give customized settings for timing, IO standards, etc, for IO pins and corresponding signals on those pins.  In most cases you can simply using the "LOC" attribute to tell the synthesis tools how to map the FPGA logic signals out to the FPGA pins.  

socjcare

Ok, thanks for the information and the guide

mjones

NP.  Let us know if you need further help.