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How to access GPMC addressing space for BBB for any custom NOR Cape or Logi Bone V2 in Starterware
Hi,
I have tried to configure GPMC bus on BBB in the following manner for 16 bit bus, Asynchronous mode:-
int main(void)
{
int blkNum;
int pageNum;
int numOfPages;
unsigned int retVal;
unsigned int eraseBlkFlg;
volatile unsigned int conf;
/* Configure and enable the MMU. */
MMUConfigAndEnable(); // TODO:- It has to be checked as to when this function is required...
/* Enable all levels of Cache. */
CacheEnable(CACHE_ALL);
/* Pin mux and clock setting */
NORPinMuxSetup();
GPMCClkConfig();
GPMCModuleSoftReset(SOC_GPMC_0_REGS);
while (GPMCModuleResetStatusGet(SOC_GPMC_0_REGS) != 1);
GPMCIdleModeSelect(SOC_GPMC_0_REGS, GPMC_IDLEMODE_NOIDLE);
/* Disable all interrupts */
GPMCIntDisable(baseAddr, GPMC_FIFOEVENT_INT);
GPMCIntDisable(baseAddr, GPMC_TERMINALCOUNT_INT);
GPMCIntDisable(baseAddr, GPMC_WAIT0EDGEDETECTION_INT);
GPMCIntDisable(baseAddr, GPMC_WAIT1EDGEDETECTION_INT);
/* Timeout control disable */
GPMCTimeOutFeatureConfig(baseAddr, GPMC_TIMEOUTFEATURE_DISABLE);
///////////Wait Pin Polarity TODO: HAs to be checked as to CS should be disabled here or not on 10/08/2015
///////////////////////////////////////////////////////////////////////////////////////////////////////////
GPMCCSConfig(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, GPMC_CS_DISABLE); // Chip Select should be disabled when the GPMC configuration is being done..
//configuration as per Table 7-27 of TRM [NOR Memory Type]
GPMCDevTypeSelect(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, GPMC_DEVICETYPE_NORLIKE); // NOR type Device selected on GPMC.
GPMCDevSizeSelect(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, GPMC_DEVICESIZE_16BITS); // 16 bit NOR device selected.
GPMCAddrDataMuxProtocolSelect(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, GPMC_MUXADDDATA_ADMUX ); // Address Data Multiplexing
GPMCDevPageLenSet(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0,GPMC_DEV_PAGELENGTH_FOUR) // ****This should not be effective as the page length will be supported in synchronous mode
//GPMCSyncWrapBurstConfig(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0,GPMC_WRAPBURST_DISABLE); // We are not using syncronous mode so this statement is not effective
GPMCTimeParaGranularitySelect(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, GPMC_TIMEPARAGRANULARITY_X2); // support for slower devices
GPMCFclkDividerSelect(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0,GPMC_FCLK_DIV_BY_4); // GPMC_CLK :- clock division by 4 i.e. 100MHZ /4 = 25MHZ TODO:- Need to confirm on this
// GPMCClkActivationTimeConfig(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0,GPMC_CLKACTIVATIONTIME_ATSTART ); // Not needed in our case, is valid for synchronous read write
GPMCAccessTypeSelect(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, GPMC_MODE_READ, GPMC_ACCESSTYPE_SINGLE); // single read access
GPMCReadTypeSelect(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, GPMC_READTYPE_ASYNC); // read type asynchronous
GPMCAccessTypeSelect(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, GPMC_MODE_WRITE, GPMC_ACCESSTYPE_SINGLE); // single write access
GPMCWriteTypeSelect(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, GPMC_WRITETYPE_ASYNC); // write type asynchornous
//configuration as per Table 7-28 of TRM [NOR Chip Select Configuration]
GPMCBaseAddrSet(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, 0); // A29:A24 = 000000
GPMCMaskAddrSet(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, GPMC_CS_SIZE_16MB); //16MB
// NOR Timing Configuration has to be completed on 10/08/2015 by Mohit Hada
// CS# de-assertion time from start cycle time for write accesses - NAND_CSWROFFTIME
// CS# de-assertion time from start cycle time for read accesses - NAND_CSRDOFFTIME
// CS# assertion time from start cycle time - NAND_CSONTIME
// No extra delay added.
// Check section 7.1.3.3.9.2 of TRM for details on this
conf = GPMC_CS_TIMING_CONFIG(NAND_CSWROFFTIME,
NAND_CSRDOFFTIME,
0,
NAND_CSONTIME);
GPMCCSTimingConfig(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, conf);
// ADV# de-assertion time from start cycle time for write accesses - NAND_ADVWROFFTIME
// ADV# de-assertion time from start cycle time for read accesses - NAND_ADVRDOFFTIME
// ADV# assertion for first address phase when using the AADMultiplexed protocol - NAND_ADVONTIME
// Check section 7.1.3.3.9.3 of TRM for details on this
conf = GPMC_ADV_TIMING_CONFIG(NAND_ADVAADMUXWROFFTIME,
NAND_ADVAADMUXRDOFFTIME,
NAND_ADVWROFFTIME,
NAND_ADVRDOFFTIME,
0,
NAND_ADVAADMUXONTIME,
NAND_ADVONTIME);
GPMCADVTimingConfig(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, conf);
// TODO:- Further description on this remains pending for lack of time
// Check section 7.1.3.3.9.4 and 7.1.3.3.9.5 of TRM for further details on this..
conf = GPMC_WE_OE_TIMING_CONFIG(NAND_WEOFFTIME,
0,
NAND_WEONTIME,
NAND_OEAADMUXOFFTIME,
NAND_OEOFFTIME,
0,
NAND_OEAADMUXONTIME,
NAND_OEONTIME);
GPMCWEAndOETimingConfig(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, conf);
conf = GPMC_RDACCESS_CYCLETIME_TIMING_CONFIG(NAND_RDCYCLETIME,
NAND_WRCYCLETIME,
NAND_RDACCESSTIME,
NAND_PAGEBURSTACCESSTIME);
GPMCRdAccessAndCycleTimeTimingConfig(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, conf);
// TODO:- Will check this????
conf = GPMC_CYCLE2CYCLE_BUSTURNAROUND_TIMING_CONFIG(
NAND_CYCLE2CYCLEDELAY,
NAND_CYCLE2CYCLESAMECSEN,
NAND_CYCLE2CYCLEDIFFCSEN,
NAND_BUSTURNAROUND
);
GPMCycle2CycleAndTurnArndTimeTimingConfig(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, conf);
GPMCWrAccessAndWrDataOnADMUXBusTimingConfig(SOC_GPMC_0_REGS,
GPMC_CHIP_SELECT_0,
NAND_WRACCESSTIME,
NAND_WRDATAONADMUXBUS);
GPMCCSConfig(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, GPMC_CS_ENABLE); // Chip Select should be enabled after the GPMC configuration is done..
}
But I do not know as to how to access the address space of GPMC hereafter.
I got a same confusion here as well but I am not sure as to how to approach this thing:-
https://e2e.ti.com/support/embedded/starterware/f/790/p/366168/1309355
I have tried to configure GPMC bus on BBB in the following manner for 16 bit bus, Asynchronous mode:-
int main(void)
{
int blkNum;
int pageNum;
int numOfPages;
unsigned int retVal;
unsigned int eraseBlkFlg;
volatile unsigned int conf;
/* Configure and enable the MMU. */
MMUConfigAndEnable(); // TODO:- It has to be checked as to when this function is required...
/* Enable all levels of Cache. */
CacheEnable(CACHE_ALL);
/* Pin mux and clock setting */
NORPinMuxSetup();
GPMCClkConfig();
GPMCModuleSoftReset(SOC_GPMC_0_REGS);
while (GPMCModuleResetStatusGet(SOC_GPMC_0_REGS) != 1);
GPMCIdleModeSelect(SOC_GPMC_0_REGS, GPMC_IDLEMODE_NOIDLE);
/* Disable all interrupts */
GPMCIntDisable(baseAddr, GPMC_FIFOEVENT_INT);
GPMCIntDisable(baseAddr, GPMC_TERMINALCOUNT_INT);
GPMCIntDisable(baseAddr, GPMC_WAIT0EDGEDETECTION_INT);
GPMCIntDisable(baseAddr, GPMC_WAIT1EDGEDETECTION_INT);
/* Timeout control disable */
GPMCTimeOutFeatureConfig(baseAddr, GPMC_TIMEOUTFEATURE_DISABLE);
///////////Wait Pin Polarity TODO: HAs to be checked as to CS should be disabled here or not on 10/08/2015
///////////////////////////////////////////////////////////////////////////////////////////////////////////
GPMCCSConfig(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, GPMC_CS_DISABLE); // Chip Select should be disabled when the GPMC configuration is being done..
//configuration as per Table 7-27 of TRM [NOR Memory Type]
GPMCDevTypeSelect(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, GPMC_DEVICETYPE_NORLIKE); // NOR type Device selected on GPMC.
GPMCDevSizeSelect(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, GPMC_DEVICESIZE_16BITS); // 16 bit NOR device selected.
GPMCAddrDataMuxProtocolSelect(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, GPMC_MUXADDDATA_ADMUX ); // Address Data Multiplexing
GPMCDevPageLenSet(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0,GPMC_DEV_PAGELENGTH_FOUR) // ****This should not be effective as the page length will be supported in synchronous mode
//GPMCSyncWrapBurstConfig(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0,GPMC_WRAPBURST_DISABLE); // We are not using syncronous mode so this statement is not effective
GPMCTimeParaGranularitySelect(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, GPMC_TIMEPARAGRANULARITY_X2); // support for slower devices
GPMCFclkDividerSelect(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0,GPMC_FCLK_DIV_BY_4); // GPMC_CLK :- clock division by 4 i.e. 100MHZ /4 = 25MHZ TODO:- Need to confirm on this
// GPMCClkActivationTimeConfig(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0,GPMC_CLKACTIVATIONTIME_ATSTART ); // Not needed in our case, is valid for synchronous read write
GPMCAccessTypeSelect(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, GPMC_MODE_READ, GPMC_ACCESSTYPE_SINGLE); // single read access
GPMCReadTypeSelect(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, GPMC_READTYPE_ASYNC); // read type asynchronous
GPMCAccessTypeSelect(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, GPMC_MODE_WRITE, GPMC_ACCESSTYPE_SINGLE); // single write access
GPMCWriteTypeSelect(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, GPMC_WRITETYPE_ASYNC); // write type asynchornous
//configuration as per Table 7-28 of TRM [NOR Chip Select Configuration]
GPMCBaseAddrSet(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, 0); // A29:A24 = 000000
GPMCMaskAddrSet(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, GPMC_CS_SIZE_16MB); //16MB
// NOR Timing Configuration has to be completed on 10/08/2015 by Mohit Hada
// CS# de-assertion time from start cycle time for write accesses - NAND_CSWROFFTIME
// CS# de-assertion time from start cycle time for read accesses - NAND_CSRDOFFTIME
// CS# assertion time from start cycle time - NAND_CSONTIME
// No extra delay added.
// Check section 7.1.3.3.9.2 of TRM for details on this
conf = GPMC_CS_TIMING_CONFIG(NAND_CSWROFFTIME,
NAND_CSRDOFFTIME,
0,
NAND_CSONTIME);
GPMCCSTimingConfig(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, conf);
// ADV# de-assertion time from start cycle time for write accesses - NAND_ADVWROFFTIME
// ADV# de-assertion time from start cycle time for read accesses - NAND_ADVRDOFFTIME
// ADV# assertion for first address phase when using the AADMultiplexed protocol - NAND_ADVONTIME
// Check section 7.1.3.3.9.3 of TRM for details on this
conf = GPMC_ADV_TIMING_CONFIG(NAND_ADVAADMUXWROFFTIME,
NAND_ADVAADMUXRDOFFTIME,
NAND_ADVWROFFTIME,
NAND_ADVRDOFFTIME,
0,
NAND_ADVAADMUXONTIME,
NAND_ADVONTIME);
GPMCADVTimingConfig(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, conf);
// TODO:- Further description on this remains pending for lack of time
// Check section 7.1.3.3.9.4 and 7.1.3.3.9.5 of TRM for further details on this..
conf = GPMC_WE_OE_TIMING_CONFIG(NAND_WEOFFTIME,
0,
NAND_WEONTIME,
NAND_OEAADMUXOFFTIME,
NAND_OEOFFTIME,
0,
NAND_OEAADMUXONTIME,
NAND_OEONTIME);
GPMCWEAndOETimingConfig(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, conf);
conf = GPMC_RDACCESS_CYCLETIME_TIMING_CONFIG(NAND_RDCYCLETIME,
NAND_WRCYCLETIME,
NAND_RDACCESSTIME,
NAND_PAGEBURSTACCESSTIME);
GPMCRdAccessAndCycleTimeTimingConfig(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, conf);
// TODO:- Will check this????
conf = GPMC_CYCLE2CYCLE_BUSTURNAROUND_TIMING_CONFIG(
NAND_CYCLE2CYCLEDELAY,
NAND_CYCLE2CYCLESAMECSEN,
NAND_CYCLE2CYCLEDIFFCSEN,
NAND_BUSTURNAROUND
);
GPMCycle2CycleAndTurnArndTimeTimingConfig(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, conf);
GPMCWrAccessAndWrDataOnADMUXBusTimingConfig(SOC_GPMC_0_REGS,
GPMC_CHIP_SELECT_0,
NAND_WRACCESSTIME,
NAND_WRDATAONADMUXBUS);
GPMCCSConfig(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_0, GPMC_CS_ENABLE); // Chip Select should be enabled after the GPMC configuration is done..
}
But I do not know as to how to access the address space of GPMC hereafter.
I got a same confusion here as well but I am not sure as to how to approach this thing:-
https://e2e.ti.com/support/embedded/starterware/f/790/p/366168/1309355
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