logi-bone clock/pulse generator and counter

lze

Seeking advice (sorry for the long post)

Hardware / software: Beaglebone Black (BBB) with Logi-bone on top as a "shield". Power is supplied via the 5v barrel DC connector on BBB. BBB is running logi-bone Ubuntu image.

Goal: Implement a counter (count square wave pulses of at minimum of 1Mhz) on the logi-bone fpga and output the result to Beaglebone Black(BBB) as a text file. The end result is that I can give logi-bone an external clock/pulse signal (via PMOD pins, for example), and I can see the counting result on BBB.

My thought:

Use the fpga's internal clock (50Mhz, or a division of it) as a test input signal for the counter. Feed this signal/pulses to the counter's input.
Assuming I can output the clock signal to a pin on the PMOD connector (e.g. PMOD1 pin 1), then connect this PMOD1 pin 1 to the input pin of the counter (e.g PMOD1 pin 2)

Verilog code for clock generator and counter (found online, modified to match parameter names/pins):

module test_clock(clock, output_clk),
 input clock;  //OSC FPGA 50 Mhz
 output output_clk;
 assign output_clock = clock;
endmodule

then, use the ucf file like below to output ("connect") the clock signal

NET clock LOC="P85"  | IOSTANDARD=LVTTL | PERIOD=20ns;
NET output_clk LOC="P112"  | IOSTANDARD=LVTTL # PMOD1 pin 1;

module 8_bit_counter
(
    input_clock,   //clock signal from PMOD1 pin 1
    reset,    // Pushbutton0, push it to clear the counter
    counter_output,
    enable //Pushbutton1, push it to start the counter
);

    input input_clock;
    input reset;
    input enable;
    output [7:0] counter_output;

    reg [7:0] counter_output;

    always @(posedge input_clock or posedge reset)
    begin
        if (reset)
            counter_output = 0;      
        else if (enable)
            counter_output = counter_output + 1;
    end
endmodule      

ucf file

NET clock LOC="P85"  | IOSTANDARD=LVTTL | PERIOD=20ns;
NET reset  LOC="P59"  | IOSTANDARD=LVTTL;  # Pushbtton0 reset
NET enable LOC="P83"  | IOSTANDARD=LVTTL;  # Pushbutton1 enable
NET output_clock LOC="P112" | IOSTANDARD=LVTTL;  # PMOD1 pin1
NET input_clock LOC="P111" | IOSTANDARD=LVTTL;  # PMOD1 pin2

Questions:
1. Can I load two .bit files (test_clock and 8_bit_counter) onto one fpga? Or I have to combine the two and generate one .bit file?
2. Is my physical connection (PMOD1 pin1 to PMOD1 pin2) correct? Based on my reading, the signals are 3.3V. I want to make sure I am damaging the board.
3. How do I output the counting result "counter_output" value to a file on BBB? Maybe I can have a Python script to open a file and "listen" to some type of connection coming in from a port?  Or maybe some other ways that I can see the result? 

I like to know if this is doable and I am on the right track before I start the actual testing.

Thank you.

jpiat

HI,

1) you cannot load two bitfiles into one FPGA. The bit file configure all the logi resources of the FPGA at once, and thus it is not possible to load part of the FPGA with one design and another part with another design.

2) There is no problem with connecting two pins of the PMODS together assuming that one is an input and one is an output.

3) If you want a communiation to happen between the logi-bone and the BBB, you 'll need to have an architecture with the wishbone bus that will allow the BBB to access the FPGA as a memory. Then you can use the Python library to read the par of the FPGA that contains the counter output. To get started you an have a look a the logi-wishbone projet on the github. You an also use the skeleton editor (www.valentfx.com/skeleton) to generate the wishbone arhiteture in whih you will then instantiate your counter.

Let me know is you need more help.

Regards,

Jonathan Piat

lze

Thanks for the quick reply.

1. Will this Verilog code work as a "combined" clock generator and counter?

module 8_bit_counter
(
    clock, //OSC FPGA 50Mhz
    input_signal, //input signal for the counter on PMOD1 pin2
    reset,    // Pushbutton0, push it to clear the counter
    enable //Pushbutton1, push it to start the counter
    output_clock, //clock signal generated by clock on PMOD1 pin1
    counter_output,
);

    input clock;
    input input_signal;
    input reset;
    input enable;
    output_clock;
    output [7:0] counter_output;

    reg [7:0] counter_output;

    //generate clock signal on PMOD1 pin 1
    assign output_clock = clock;
   
    //counter
    always @(posedge input_signal or posedge reset)
    begin
        if (reset)
            counter_output = 0;     
        else if (enable)
            counter_output = counter_output + 1;
    end
endmodule     

ucf file

NET clock LOC="P85"  | IOSTANDARD=LVTTL | PERIOD=20ns;
NET reset  LOC="P59"  | IOSTANDARD=LVTTL;  # Pushbtton0 reset
NET enable LOC="P83"  | IOSTANDARD=LVTTL;  # Pushbutton1 enable
NET output_clock LOC="P112" | IOSTANDARD=LVTTL;  # PMOD1 pin1
NET input_signal LOC="P111" | IOSTANDARD=LVTTL;  # PMOD1 pin2


2. I don't know how wishbone works. I'll study/research.

lze

Read and tried the logi-wishbone info/demos, all worked as indicated in the documentation.
 
If I understand the concept correctly, I can send the counter_output to a memory location on the fpga (e.g. 0x000A), then use either python or C (e.g. read_wishbone) to retrieve the content (which is the counter_output value) from memory location/address 0x000A.

1. How do I send the counter_output value to a memory address?
2. How do I know/choose which memory address to use?
3. Wishbone uses 16-bit, does that mean each memory address can also hold 16-bit data? e.g. if I have a 16-bit counter, it means I can write and read once to get the counter_value, correct?

Thanks.