Development tools (SystemC)

lewismjx

Hi,

I wanted to do a pet project where I was moving some code that I had written for a GPU onto the LogiPi.

This is pretty simple numerical function, in the past I've read up on SystemC/ImpluseC - I was just wondering if anyone knew of similar tools that I could use with the Logi-Pi ??  i.e. be able to synthesize something from almost C/C++ onto the FPGA board.

 

Thanks,

Mike

mjones

@lewismjx

I know that there are some very expensive options from xilinx and altera, such as HLS for xilinx.  http://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html

For low cost options you could look at myHDL or migen.  Jonathan wrote a very nice writeup taht talks about these high level tools:

http://www.element14.com/community/groups/fpga-group/blog/2014/10/28/alternatives-to-vhdlverilog-for-hardware-design

madscientist_42

To the best of my understanding there's several tools out there- but most of them require at least the free VHDL tools from Altera and Xilinx to produce the synthesis proper.  (WebPack does work for many things- and if you've got one of the supported FPGA's for it, you're going to find it works "okay" for most things you might do on Xilinx, for example.  And...for free no less...)

myHDL's one.  If you're familiar with Python, it's a front-runner, because you can specify some pretty impressive HLS work with it on the cheap.

If you're into Haskell, there's several differing options to transform a Haskell functional program into the same.

CLaSH
Kansas-LAVA

Haskell's a bit different than many are used to.  It's a functional programming language with all that this entails.  It will allow you some unique options for expressing things, if you're familiar with Haskell or are willing to learn a bit of it.

If you're willing to work with some experimental stuff, you can express real C/C++ algorithms and code as synthesizeable VHDL. 

AHIR

AHIR is a bolt-on to LLVM that allows you to feed clang code into it and produce VHDL as a feed into WebPack or whatever so long as you don't get TOO fancy with your coding.  It was used in an experimental Click modular router to Net-FPGA system mapping that was actually a lot more impressive than you'd think for it.  It does have a few limitations, but it's really much more like C/C++ coding (which is the HLS that a full license to Vivado or the OpenCL extensions from Altera bring to the table...) than the previous tools which were more C-like VHDL mappings.  You could do some coding, but it was limited to just what VHDL normally allowed you for it.  This is different.  You might be able to take other mappings into LLVM and use them to feed into AHIR, but this isn't supported yet.

mjones

@madscientist_42  Thanks for your input!  I was not familiar with Clash or AHIR.  It is good to seem alteranative HLS options and especially nice for general users who do not want to dive directly into HDL.

Cheers!