Logi-Bone and high speed 40msps ADC

Iceage

Hi,

I am looking at interfacing a 10bit 40msps ADC to my Logi-Bone and I would like to ask if anyone on here have considered which interfaces on the Logi-Bone to use, if this is electrically possible at this speed ?

There are LVDS ADC devices (which are considerably more expensive) than the standard parallel ADC'c which are widely available but it may be that to use such a device with a Logi, I may need to go down the LVDS route.

I intend to decode a 1Mhz bw RF signal in the FPGA using an Xilinx Fir IP core and before I draw up a schematic for a PCB design to piggy back on the Logi, I wanted to garner other peoples thoughts and opinions.

Kind regards,

Andy

jpiat

Hi,

this is something we would really like to see happen. 40Msps with a parallel interface could be possible on the LOGI-Bone using the two PMODS (16 bit in total). The camera we are using feeds a 24Mhz clock back to the FPGA, so 40Mhz should be possible (but i never tried). On the LOGI-Bone, the GPMC interface carry a 50Mhz clock on the stacking connector with no problem. Do you have a component reference for a 40Msps parallel ADC ?


We are investigating LVDS for an ADC, and it could work for a single channel at 40Msps. The only problem is that for more than each additional channel you'll need an additional LVDS pair.

Regards,

Jonathan Piat

mjones

Hi Andy,

Sounds like a cool project.  Maybe we can help with designing a PMOD compatible PCB based upon a good looking ADC. It would be nice find a a good general high bandwidth ADC that would work for many applications, not just your RF application.  LVDS would be optimal especially for the lower pin availability of the bone, but of course cost is important to.   Also, LVDS is a great excercise for the FPGA! 

Maybe you can  post some notes on chips you have looked at and I can take a look at some alternative ADCs as well.  Hopefully we can land on a good one!

Iceage

Hi Guys,

LVDS is too expensive for the project that I have in mind. I have been doing a little research this week and apologies for the late reply but do you think that we could use the Arduino header for this purpose using a parallel ADC such as this one from the respected Analog company ? I have read the Logi-Bone documentation and looked up the schematic but I am unsure as to how many directly connected FPGA pins there are on this connector selection. Maybe we have enough GPIO's for the ADC on the BB header but if we used the Arduino header, the project could encompass both the BB and RPI too  The PMOD's can be used but I'd like the project to piggy back on the Logi rather than be an 'extension'.

Thoughts and feedback appreciated.

Kind regards,

Andy.

mjones

Hi Andy.

So parallel it is.  

The main issue on the current design is that we ran out of pins and the arduino shield took the brunt of hit on this.  We worked the design trying to scrape up as many IO as we possible could, which meant that we had to share some of the Arduino pins with other pins, including the FPGA configuration pins and sharing with teh bone SPI pin (to access arduino dircectly from bone).  Most of these pins are fine to use once the FPGA has been configured, but care must be taken that the pins do not conflict during configuration.  

Do you have a ADC part in mind?  8 bit parallel I assume?

chuck_c

Don't want to hijack the thread, but I'm also very interested in this application using the AD9203 (10-bit ADC). It's been a long time since I coded an FPGA, but I would like to grab sampled chunks of data (say a 4kB chunk) onto a Beagle Bone or Raspberry Pi using an AD9203 + FPGA. Do you think this would be possible?

Thanks,

Charles

mjones

Hi @chuck_c ,

@Iceage does this chip work for you as well?

Yes, very feasible, though on the Rpi you would not be able to stream the data as the SPI port would not be able to keep up with ADC data (at 40MSPS).  But you could set up a buffer using the SDRAM or BRAM.  I am in the middle of doing some designs, but can look at doing a prototype and sharing the desing files once complete.  For ease of prototyping, it would be easiest to use a dual pmod, but the design could be moved to arduino eventually. 

Do you have any specific requirements for how the ADC is setup on the board?  

chuck_c

Thanks for the reply, @mjones . Sorry I've trailed off a bit, but I've just been reading more about this to try to figure out the best setup for my application. It's tough for me to understand what should be done on the FPGA vs. the microcontroller, though. This chip:

http://www.ti.com/product/afe5801#descriptions

has most of the signal processing I need, although I only need one channel despite it having 8. It uses LVDS outputs. I think for my application, I would send a rising edge from my microcontroller that would begin sampling for a specific amount of time (repeating at low kHz frequency range). For each repetition of this clock (or group of repetitions), I would want to sample a specific amount of data (~5000-6000 samples), transfer the samples to the computer, process, and then continue sampling more. I'm trying to understand what role the FPGA would play in this scenario. On receiving the rising edge, would it somehow negotiate the LVDS into a local RAM that could be read at the convenience of the microcontroller?

mjones

Hi @chuck_c ,

That is a very expensive part ($46-63@1).  What exactly are you looking for from this part?  Sampling rate, variable gain, differential input, LVDS or all of the above.  What kind of sensor would you be sampling?  It may be cheaper to build a discreate VGA with a more standardized ADC.  

I was thinking of designing something pretty low cost/generic that users could interface with many different types of applications and would use a lower cost parallel interface for the higher sample rates(40Mhz+).  I havn't had time to do a good market survey yet, but hope to soon.  

The FPGA could act in any number of ways.  In the simplest fashion it would act as a buffer mechanism for the Pi/Bone.  It would sample the data and buffer it into SDRAM that could be accessed from the Pi/Bone.  Alternatively you could do any kind of pre-processing on the data including FIR, IIR DSP filtering and such.

Cheers,

Mike

chuck_c

Good point about the price.

I am trying to build a single-element pulse-echo ultrasound device, so this chip pretty much has the signal chain implemented. I would be sampling a single element transducer. I own some other devices that use this chip in a multi-channel fashion, and it's not the bee's knees or anything, so I'm not set on it. Also, I don't need eight channels and keeping cost down is a major goal, so I'd be willing to go the roll-your-own route on the VGA. Building this in a few months time frame with somewhat limited resources is another major goal, so I am trying to keep things as simple as possible. That drew me to this chip somewhat, since I have some other parts of the design that I will need to work out (power, software control, transmit/receive circuit, etc..)

I think I'm understanding the role of FPGAs a little bit better in these kinds of systems. I programmed VHDL when I was in college for a few applications, but never really implemented a full integrated system...and that's been 10+ years ago at this point The reason to use it as a buffer is because then the software on the Bone could just off-load the entire buffer as necessary rather than having to directly grab the samples at whatever your rate is?

In any case, the AD9203 would likely be very suitable for the application I have in mind. I can see how that would be a really great addition to the LogiBone repertoire.

mjones

Hi @chuck_c

I see.  It sounds like in the end you will want to integrate all of your circuitry onto a single expansion board for the bone in the end?  

What I can do is focus on getting a prototyped high speed ADC peripheral that you could prototype with you could then switch out to your own custom PCB with integrated components, including ADC possibly.

I did a quick survey of some of the ADCs available in both parallel and LVDS.  

https://docs.google.com/spreadsheets/d/17Q7nOV3jm_teprBrz8QsyzppGDWi-I9Fw6RKtQamn1M/edit?usp=sharing

What would awesome is if we could find a chip that supports LVDS and parallel which could be used in either manner on the same dev board.  I have never heard of NXP ADCs but they offer a very low cost LVDS/Parallel 65Mhz ADC @$8.80.  I did not too closely at the deep specs yet, but at face value it has a ton of bang for buck.  I will keep searching to see if I can find more feasible LVDS/Parallel chips. 

Anyone used NXP ADCs?  I imagine it may not be completely on par with linear tech, analog devices, but it may serve the purpose of a low cost high functioning part for prototyping.  Anyone have other suggestions?

Feel free to add the spreadsheet I started with more options.

Cheers,

Mike

Iceage

Hi all,

@mjones That ADC that you have found is a very interesting component. I have taken a good look and it looks like it is a parallel LVDS device We don't have enough IO on the Logi for one of those, do feel free to correct me though. NXP are a great company I have a few of their CPU development boards.

Keep up the excellent Serial LVDS ADC hunt up that was a nice find!

I have started a schematic in Geda and it is nearly finished, this is based the AD9203 (apologies the link was hidden on my post Nov 9th)  running with a 40Mhz clock and will utilise the 3.3v initially from the PMOD but I have also provisioned an extra 5v-3.3v supply which can be fed via a mini usb if we run into supply restrictions on the 3.3v rail- A jumper can be used to select the feed - A little more research needed here. I will try to get it finished in the next day or two and will post it here for consideration/comments.

Hope that is helpful.

Cheers,

Andy

mjones

@Iceage  Ahh, indeed parallel LVDS.  Interesting that that the parallel devices cannot support serial.  I did some more scrubbing to see if I could find any lower cost serial LVDS.  The LTC2264CUJ-12#PBF  is the lowest cost serial LVDS device I could find >=@40Mhz = $18@100.  The nice thing is that it has 2 channels which could be useful for many applications.  Still quite a bit more pricey than parallel though.  I could do a prototyped design if anyone is interested.

Good to hear you are making progress on the AD9203!  Let me know if you can use a hand on design review or PCB layout.

On another note.  We are also working on an LVDS camera prototype.  We can post the current design if anyone is interested in giving feedback or trying it out.

Cheers,

Mike

SquareOne

yes i would be interested in your LVDS camera design .

mjones

Hi There,

I will post the LVDS design in the logi-boards repository on github shortly.  

madscientist_42

Did anyone get anywhere with the notion of a higher-speed interface to all of this?  I'd love to get a higher sample rate A/D and D/A on a single board for one of my projects.  The LogiPi makes for a nifty solution that's not pricey for people to experiment with FPGAs.  Otherwise, you're looking at double/triple for the appropriate hardware to do this stuff with something like Parallella's board and their mezzanine card- or double that expense if you're using a ZedBoard or the Xilinx eval board for the Zync.

mjones

VFX has not had a chance to go hear yet.  We are currently finishing MFG, FCC/CE testing for the next LOGI mfg run.  It was quite the processes getting up to speed on EMC!  The boards have passed and will be to E14 soon.  

We do have a working LVDS camera in development which will be our next peripheral.  I think that a high speed ADC will be next.  

@Iceage did you get something going with your AD9203 proposal?

Cheers.

madscientist_42

Cool.  I figured it'd be a bit before you could get something out.  While the sata connector makes it easier, I kind of lost access to my short-term ability to leverage that for myself...so I was hopeful I could just wait a smidge and see if someone would at least work on the start of something like that.

Iceage

Hi Guys,

Apologies but I got distracted with the front-end design that I want to interface the ADC to.

Anyways I have attached what I have so far but must admit I have now moved away from gEDA Schematic and started using Upverter instead. You may want to check it out. Brilliant stuff from the guys there!

If you wish me to continue I can draw it up there real soon.

Hope it is of help.

In addition you may want to check this out; http://newae.com/files/openadc-datasheet.pdf

I had it in my bookmarks for further reading/building and it will suit the PMOD's on the Bone.

@mjones The schematic is a jpeg and the forum is informing me that Uploaded file type is not allowed, can you help ?

Cheers,

Andy.

mjones

@Iceage

Thanks for the update.  I have added a new upload plugin.  It seems to work for me.  Let me know if you hit an issue.  Would be interested in seeing your schematic.   

OpenADC looks like a nice option for high bandwidth stuff and great to see it supports dual pmods! 

Iceage

@mjones thanks for this and to just push the envelope, I have just done it from my iPad!

It'll be great to hear your thoughts, my design will feed the ADC from a logarithmic detector.

Cheers,

Andy.

Iceage

In addition, I am currently researching a 3.0v low dropout low noise regulator for the analog supply (AVDD) for the design. 

Here is what I am proposing

http://uk.farnell.com/analog-devices/adp150aujz-3-0-r7/150ma-ultra-low-noise-ldo-3-0/dp/2376919

Thoughts ?

mjones

Hi @Iceage

What kind of an application are you targetting?  It sounds like RF, maybe RSSI?  

Looks like a good start on your design.  Yeah, I have heard good things about upverter - I'll have to give it try one of these days.  Does it have import tools for altium? 

Keep us posted on your progress.

Cheers!