LOGI Stack Overview
The key to successfully using an CPU/FPGA co-processing system is allowing them to transparently and efficiently read and write data between the CPU and FPGA. The LOGI stack consists of software, drivers, firmware and HDL that allows users a seamless interface between the FPGA and the host CPU when using the LOGI development boards. A block diagram of the LOGI stack can be seen below.
CPU Side communication
CPUs generally have hardware communication peripherals such as GPMC (BeagleBone), SPI(Raspberry Pi), and other standard parallel and serial interfaces. It is optimal to use these hardware interfaces in conjunction with the CPUs DMA (direct memory access) hardware, if available, to offload CPU usage and transmit data at maximum rates. This is easily possible by using C or lower level languages to configure the CPU registers and then transmit and receive data via the CPU hardware. ValentF(x) has created efficient low level interfacing drivers for the BeagleBone and the Raspberry Pi with easy read and write APIs to receive and transmit data to and from the CPU. Users can use read and write commands to directly access memory mapped registers, memory and user space applications within the FPGA.
For additional ease of use and access to vast adn easy to use libraries ValentF(x) implemented the use of Python within the library stack. ValentF(x) has created C to python wrappers libraries that allows users to develop their CPU/FPGA applications in Python on Linux systems on the Raspberry Pi and the BeagleBone.
FPGA side communication
The wishbone bus architecture is used on the FPGA to allow multiple address mapped peripherals and modules to be accessed from the CPU. Wishbone allows for any number of wishbone peripherals to easily be attached to the system bus and can send and receive data at a rate which is limited by the communication hardware on the CPU. In order to directly communicate from the CPU to the wishbone bus a wishbone wrapper is required that translates the wishbone communication standards to the CPU host communication protocol being used. ValentF(x) currently has stable wrappers implemented that allows efficient communication between the Raspberry Pi and the BeagleBone to the FPGA.
Scalability of the LOGI Stack
The LOGI stack architecture can be used to support any future CPU host/FPGA hardware as the LOGI ecosytem evolves. The wishbone bone bus can be wrapped to support direct communication with future supported CPU hardware as needed.
Experimenting with the LOGI Stack
Users can easily begin experimentation on using the LOGI Stack by running the LOGI-Apps which are installed on the pre-configured LOGI images for the Raspberry Pi and BeagleBone. The LOGI Wishbone project contain the C and Python APIs and a configured FPGA bitstream that demonstrates the usage of read/writes to registers, memory and a PWM LED core on the FPGA.
Where To Go From Here
See the specific project pages that will give you full details about the apps that are run in this project.
Have a look at the documentation for other projects and or our drivers and software to kickstart your own projects.