LOGI Bone User Manual
LOGI Bone - User Guide
Bringing FPGA Technology to the BeagleBone
The LOGI Bone is the first FPGA development platform that has been optimized for use with the BeagleBone. The LOGI Bone adds FPGA flexibility and capability that allows the BeagleBone to be easily morphed into a myriad of digital applications. The FPGA/Processor combination using the LOGI Bone creates an incredibly powerful and versatile digital canvas for users to create their imaginative digital designs.
This user manual is intended to contain any needed information to using the FPGA in conjunction with the Beagle Bone (black or white). For documentation on the BeagleBone the user can find any relative information and documentation on the Beagleboard.org site.
- FPGA: Spartan 6 LX9 – TQFP144 Package - XC6SLX9-2TQG144C
- Plug and play interfacing the BeagleBone
- LOGI Stack of firmware, drivers and so to make interfacing to the FPGA easy
- Arduino Shield expansion allowing for more than 200 existing plug in hardware modules
- Pmod compatible headers allowing for more than 50 existing low cost hardware modules
- 4 layer optimized design to support maximum performance of high bandwidth applications
- Length tuned GPMC, SDRAM and LVDS signals for high performance applications
- 50 Mhz MEMS oscillator
- 2x Push buttons
- 2x DIP Switch
- 1x High bandwidth LVDS connector expansion port
- 32 FPGA IO available through Pmod and Arduino headers
- 2x Digilent Inc. Pmod ports supporting 59+ plug and play hardware modules
- 1x Arduino Header supporting 200+ Arduino Shield modules
- Optional I2C, SPI access from the BeagleBone
- 10x LVDS pairs routed as: 100 ohm differential, 50 ohm single-ended
- 256 Mb SDRAM
|External Vin Connector|
|Voltage Max.||Voltage Nominal||Voltage Min.|
The LOGI Bone can be powered through the BeagleBone connector or from the on-board external power connector. If powering the LOGI Bone from the BeagleBone connector, it is recommended that a 1A external power supply be used to power the BeagleBone. Most FPGA applications will not require the use of a separate external power supply to power the LOGI Bone, but it is up to to ensure that the FPGA applications will not over-load the BeagleBone power rails which will cause brown-outs and or system failures.
All current LOGI applications can be run while being powered only from the BeagleBone connector. The user should test newly designed applications to ensure the FPGA load falls within acceptable values. Information relevant to the BeagleBone system power requirements can be found the BeagleBone wiki.
The LOGI Bone uses LDO regulators to supply 3V3 and 1V2 to the onboard peripherals and the FPGA in order to reduce costs. The power distribution was designed to allow maximum dissipated heat to the internal and external power planes. If very high demand applications are designed testing should be done to ensure that the LDO regulators are not overheated due to the heavy loads. All current applications have been tested including the heavy load of the bitcoin mining applications and no over-heating issues have been found.
The LOGI Bone was designed to allow for easy expansion to a maximum number of off-the-shelf hardware modules. The LOGI Bone uses Digilent Inc. Pmod expansion ports and an Arduino Shield expansion port that give users a plug-and-play experience with over 250 off-the-shelf hardware modules. An LVDS port was added to board to be used for maximum bandwidth applications. There are 10 LVDS pairs routed on the board that are all length matched. These interfaces will allow for a multitude of varying applications to be implemented on the LOGI Bone. Due to the high amount of flexibility of the board, some pin functions are shared between different peripherals. This section will cover the details of the peripherals and how to use to while eliminating any pin conflicts.
Top Level Block Diagram
LOGI Bone Board Diagram
BeagleBone P8/P9 Connector Pin Usage
Below is an diagram that shows the pins that are used on P8/P9 of the BeagleBone. The names of next to the pins correspond to the nets that are used in the schematics of the LOGI Bone design and are indicative of the given pins function.
For detailed pin connections you can download the latest schematics from the LOGI Github respository.
The BeagleBone Black design shares pin functionality and allows for multiplexing of specific functions on each pin. The BeagleBone Black SRM section "7.1 Expansion Connectors" lists the pin sharing functionality.
BBB Peripheral Priorities in the LOGI Bone Design
Priority of peripherals was designed for 1) GPMC high bandwidth interface 2) HDMI using the LCD pins.
The GPMC bus allow for a high bandwidth interface between the FPGA and the ARM processor. The current LOGI GPMC driver support a bandwidth of up to 70 MB/s. The GPMC bus allows for many high performance applications utilizing this high speed link and was designed as high priority in the LOGI Bone design.
The HDMI output on the BeagleBone black allows for a standalone computer experience for users. The LOGI Team has plans to fully utilize the desktop feature that the HDMI video output enables. The LOGI Team has designed Virutal Components that give the LOGI Bone users a graphical interface to and from the FPGA using the HDMI output of the BeagleBone Black.
EMMC with the LOGI Bone / BBB
Unfortunately, the EMMC port is shared with the GPMC bus and cannot be used simultaneously with GPMC functionality. It is possible for the user to implement the EMMC functionality, but requires that the SPI port be used as the communication interface between the FPGA and the BBB. The SPI interface is much lower bandwidth than the GPMC, but will allow for EMMC, HDMI and LOGI Bone FPGA functionality to occur simultaneously.
Pmod Expansion Port
There are 2 x Digilent Inc. Pmod ports populated on the LOGI Bone. The Pmod ports allow for a wide array of COTS modules to easily be interfaced with the LOGI Bone. A listing of all currently available Digilent Inc. Pmod modules can be found on their site. More 3rd party Pmod modules can be found by searching on google.
The LOGI Bone has only 2 Pmods and the LOGI Pi has 4 Pmods. The LOGI Bone design differs from the LOGI Pi in that there were extra pins needs to implement the GPMC parallel bus between the FPGA and the BeagleBone.
Arduino Expansion Port
An Arduino header is used to expand the on-board capability of the LOGI Bone with more than 200 COTS arduino shields currently on the market. The LOGI Bone arduino header supports UNO, DUEM and DUE Arduino headers. Note that only 3V3 Arduino Shields are supported as there is no logic level translation on the LOGI Bone board. The latest Arduino shield specification states that arduino shields should be designed using the IOREF pin that switches the LOGIc level of the Arduino shield to support the UNO (5V) or the DUE (3V3). It is the users responsibility to ensure that shields that are to be used with the LOGI Bone are 3V3 LOGIc.
- "Shields will be compatible with both the board that uses the AVR, which operates with 5V and with the Arduino Due that operates with 3.3V."
- "IOREF. This pin on the Arduino board provides the voltage reference with which the microcontroller operates. A properly configured shield can read the IOREF pin voltage and select the appropriate power source or enable voltage translators on the outputs for working with the 5V or 3.3V."
The Arduino header can optionally be accessed directly by the BeagleBone either by direct shared connections or indirectly through the FPGA. This allows for direct use of the BeagleBone's SPI, I2C, UART hardware to directly talk to the Arduino shields. Alternatively the shields can be accessed directly by the FPGA which can then be accessed by the BeagleBone.
See ADC Functionality and Wiring for details on the Arduino ADC pins.
ADC Functionality and Wiring
LOGI Bone RA3 and later revisions only
The LOGI Bone implements 6 ADC input pins that interface directly to the BBB ADC pins. A voltage divider is used on these pins to drop the voltage of the Analog voltage to within the limits of the BBB ADC voltage specification of 1.8V.
Additionally the user may jumper the Arduino AN0-AN6 pins to a Pmod ADC so that the FPGA can directly access the ADC values. P6 is an unpopulated header on the LOGI Bone that the user can wire directly to a Pmod port of FPGA ADC access. Digilent Inc. Carries a variety of ADC Pmod devices.
LVDS Expansion Port
The LVDS connector on the LOGI Boards were not implemented to communicate with SATA devices, but to provide an easy to use, low cost LVDS expansion port. SATA interfaces are very widely used which make the cables and connectors very low cost and easily accessible.
A high bandwidth interface was designed onto the LOGI Bone using a SATA connector. SATA connectors are very low cost and SATA cables are readily available and cheap. The SATA connector allows for a low cost impedance controlled connection to externally designed modules that are designed using a SATA connector. The LOGI Team anticipates designing high bandwidth modules such as LVDS camera, LVDS ADC, etc.
Two differential pairs are routed to the SATA connector. The differential pairs are routed as 100 ohm differential and 50 ohm single ended pairs. The differential pairs are matched in length to within .015" length from each other.
LVDS signal usage
Additional LVDS differential pairs were routed on the board to allow for experimentation and work with further multi-channel LVDS applications that require more than is available with the SATA connector. Eight additional differential pairs were routed to Pmod3 and Pmod4 connectors on the board. The differential pairs are routed as 100 ohm differential and 50 ohm single ended pairs. The differential pairs are matched in length to within .015" length from each other. These additional differential pairs were also routed to match the length of the SATA differential pairs so that they could be used in the same applications as needed.
The Pmod connectors are not optimized for use in LVDS application based on the differential signal length the is created by the connectors being 90 degree angles. The upper and lower rows on the Pmod connector do NOT match in length and if the Pmod connector is to be used this differential length in path should be taken into account.
The Pmod connectors are not optimal for differential signals as they are not capable of maintaining the differential impedance based on the large separation of the signal throughout the length of the connector. It is possible to minimize this mismatch by replacing the Pmod connectors with low profile .100" vertical headers that will shorten the path of separation therefore minimizing the impedance mismatch and allow for higher bandwidth interfaces. For optimal performance using the LVDS signals on Pmod3 and Pmod4 it is recommended that LVDS signals be directly soldered to the header pads to eliminate the impedance mismatch that occurs throughout the connector.
Push Button Usage
Two push button switches are provided on the LOGI Bone. The pushbuttons are configured active high and an discrete 10k ohm pull-up resistor is populated on-board to eliminate the need for configuring and used the on-chip pull-up resistors.
DIP Switch Usage
A two position DIP switch is used on the LOGI Bone. It is anticipated that the DIP switch be used for mode control and other general purpose usage.
Two general purpose LED's are used on the LOGI Bone. Due to the limited pin availability on the FPGA TQFP package the LED pins are also shared with two rarely used PWM inputs on the Arduino Shield (RA2.1 only).
A unpopulated JTAG header is available on the LOGI Bone. The JTAG header is contains the Digilent Inc. 6 pin function pinout and is a .100" 6 pin header. The Digilent Inc JTAG adapters or Xilinx flying lead adapters can be used to interface with the FPGA through the JTAG connection. The JTAG connection allows for direct programming FPGA or onboard Flash memory, additionally chipscope can be used for deep debug and analysis.
Linux Images for the LOGI Bone
Pre-built LOGI Image
You can download a pre-configured image with all of the drivers needed to get started with communicating between the LOGI Bone and the BeagleBone black. There are some basic demos that you will be able to run to test the communication and use as a base to begin developing your own applications or downloading the LOGI applications and running them on your LOGI/BeagleBone system
What is on the image
Kernel module that supports GPMC bus and the interface between the BBB and LOGI Bone
LOGI loader - FPGA bitstream loader to dynamically load bitstreams from the BBB
Git repository setup to access pull the latest demos for the BBB and the LOGI Bone (coming)
Download the Latest LOGI Image
You can access our pre-configured Logi image that contains everything you need to get going with the LOGI boards.
Latest LOGI Bone Ubuntu image: http://valentfx.com/doc/logi-image/logibone/logibone_150429_ubuntu-14.04-console-armhf-2014-08-13.img.zip user: ubuntu pass: temppwd
Loading the Image
The image requires a minimum of 4GB SD card be used.
The image can be loaded on an SD card on windows or on a linux system. For windows it is recommended that you use Win32DiskImager and for Linux use USBImageWriter or by using the command line disk utilities. Mac users can use Pi Filler to copy the downloaded image to an SD card.
Create Your Own Linux Image Compatible with the LOGI Bone
Getting the latest Pre-built Ubuntu or Debian image for the LOGI Bone (Recommended)
Alternative to building the kernel source to create your image the user can access pre-built Ubuntu or Debian images for download from the http://elinux.org/BeagleBoardUbuntu or http://elinux.org/BeagleBoardDebian . Within these linked page see the sections labeled: "Get prebuilt image" for the latest download links. Then follow the instructions in the given section for writing to your SD card.
Jump to the sections "Install the LOGI Tools and Install the LOGI Apps" to finish creating your image.
Create a Debian or Ubuntu image for the LOGI Bone (More Painful Option)
There is no difference to setup a beaglebone-black or beaglebone-white. Debian and Ubuntu image published after June 2014 are compatible with LOGI Bone with no change.
Debian/Ubuntu image with version suffix greater than bone60 are compatible with the LOGIbone out of the box, jump directly to step "Install the LOGI tools"
Debian/Ubuntu image with version suffix greater than bone58 are compatible with the LOGIbone but will require to be updated for compatibility with latest tools
Debian/Ubuntu image with version suffix lower than bone58 are not directly compatible with the LOGIbone latest tools. Mail email@example.com if you need to use version prior to bone58
Distributions with kernel version prior to bone61 will require the following steps. The following will need to be run on an x86 Linux based machine. This won't work on the BeagleBone itself.
Install kernel source
edit version.sh and change the BUILD variable with the bone suffix matching your distribution (uname -a in a terminal on your BeagleBone)
This may take some time (hours). When it completes, you should have new files in the deploy folder. Mount your sd card on your PC (simply insert sd card in reader on your PC) and update the kernel. Copy the .zimage file in place of the older kernel (in boot partition or /boot in rootfs partition) and then
update the device tree files (dtps on boot partition or dtbs in /boot on rootfs partition) using the *dtbs.tar.gz archive.
Install the LOGI Tools
Clone the LOGI tools repository on your beaglebone or download the zip file on https://github.com/fpga-logi/logi-tools and copy it to your beaglebone filesystem. Run the install_logibone.sh script as sudo.
What "install_logibone.sh" does
- Installs the LOGI loader which is used to configure the FPGA
- Writes the contents of the EEPROM with the proper device tree configuration that will properly configure the BBB peripherals and IO upon each boot
- Updates needed libraries and tools
- Installs C libraries
- Installs the LOGI python libraries and tools to read and write from the BB
Note that this will update the EEPROM contents with appropriate device tree overlay information that will be used to automatically setup the device tree each time the BB is booted.
Install the LOGI Apps
f you are creating your own image with the LOGI tools, you will need to first pull the LOGI apps code into your home directory. You can use git or transfer the files using SSH.
To get the latest LOGI apps from the LOGI github repository into your home directory use the following commands:
Note that the git clone command checks out the remote branch "LOGI Bone" of LOGI apps which contains all of the specific code and drivers needed to run the LOGI applications.
Device Tree Requirements
The Device Tree (http://www.devicetree.org/Main_Page) is used by the BeagleBone blacks to properly configure and mux the onboard hardware peripherals that will be used for a given configuration. In order for the LOGI drivers to properly function the BBB must be configured with an appropriate device tree overlay to configure the GPMC,SPI, I2C etc. For specific information about the device tree, how it works and how to create your own device tree overlays, see adafruit's existing guide or Hipster Circuit blog posts.
Full LOGI-Bone support is included in beaglebone-black mainline kernel since bone53 but latest support for LOGI-Bone tools is complete since bone60. Beaglebone-black running kernel prior to bone60 will require to be updated following instructions of "Create a Debian or Ubuntu image for the LOGI Bone" Latest changes in device-tree configuration allowed to use SPI for the FPGA configuration instead of bit-banging the protocol. This also allowed to move configuration code from kernel-space to user-space thus allowing to update it without the need to recompile the kernel module. As a bonus SPI communication with the FPGA is now also possible.
Kickstarter Early Bird Boards auto device-tree setup
Kickstarter ealry-birds boards require to install the logi-tools (following instructions at "Install the LOGI Tools") to properly flash the on-boards configuration EEPROM and install the required binaries (logi-loader).
Example Device-Tree overlays and scripts
The LOGI device tree overlay files and setup script can be found in the LOGI Kernel github repository. Since bone53 the LOGI-Bone Device-Tree configuration is also integrated to mainline kernel and thus can be found at : http://github.com/RobertCNelson/bb-kernel.
LOGI Bone template driver
The LOGI kernel repository hosts the source for a template driver for the LOGI Bone. This driver exposes one interfaces in the /dev folder.
- logibone-mem : The /dev/logibone-mem interfaces gives access to the full address space of the FPGA when using a wishBone based architecture. This interface can be used for communication with the logic with bandwidth between 4MB/s and 70MB/s depending on the amount of data transferred and device-tree configuration. The default device-tree configuration uses conservative settings to guarantee data integrity and compatibility with all logi-projects. Only more agressive settings (burst enabled and timing revised) will allow to reach the max advertised bandwidth. This interface will suit the need of most users to get a basic but fast communication running with the FPGA.
The template driver is modular enough so that you can use its source code to start writing your own driver for a specific application.
Compiling The Template Driver
To compile the template driver you first need to install the kernel source of your distribution one your linux machine. The following instruction will work for a Ubuntu machine (tested on 12.04 LTS) compiling for a Ubuntun distribution running on the beagleBone.
Installing a the tool chain
The default tool chain to cross-compile the linux kernel for the beagleBone is Linaro. You can install linaro on a Ubuntu machine by running the following command.
Installing the kernel source
The kernel source can be installed from git. The following command will run to install kernel 3.8.13. You may adapt the command for a new kernel/older kernel.
If everything goes well you should en-up with a KERNEL directory containing the kernel source and produced binaries.
Installing and compiling LOGI Bone template driver
The source of the kernel driver can be clone from the LOGI kernel repository.
Now you have to edit the build_module.sh with the path of your tool chain (arm-linux-gnueabihf if you are using the Ubuntu kernel and Linaro tool chain) and the path of your kernel (should be the KERNEL folder of the repository installed in the "Installing the kernel source" step).
Once the build_module.sh file is edited you just have to do a
and you should end up with the *.ko file of the kernel module in the LOGIBone_ra2 folder. This will produce to modules suffixed _dma and _dm. The _dm can expose more bandwidth but requires more processor involvement, the _dma module uses the EDMA which performs transfer in parallel with computation. The _dma exposes less bandwidth for small transfer but free the CPU while transferring, for large transfer the EDMA method will work better.
Creating Your Own Template Driver
Let say you want to use the FPGA as a frame buffer for a connected camera, you can design your own driver based on the template driver and implement a frame buffer driver. Designing your own driver will help you get the best performance for a specific application but the template driver exposes enough functionality so you can start prototyping without messing with kernel module programming.
Software and Hardware API from the LOGI Pi to the Raspberry Pi
The LOGI Stack Overview
The key to successfully using an CPU/FPGA co-processing system is allowing them to transparently and efficiently read and write data between the CPU and FPGA. The LOGI stack consists of software, drivers, firmware and HDL that allows users a seamless interface between the FPGA and the host CPU when using the LOGI development boards. A block diagram of the LOGI stack can be seen below.
CPU Side communication
CPUs generally have hardware communication peripherals such as GPMC (BeagleBone), SPI(Raspberry Pi), and other standard parallel and serial interfaces. It is optimal to use these hardware interfaces in conjunction with the CPUs DMA (direct memory access) hardware, if available, to offload CPU usage and transmit data at maximum rates. This is easily possible by using C or lower level languages to configure the CPU registers and then transmit and receive data via the CPU hardware. ValentF(x) has created efficient low level interfacing drivers for the BeagleBone and the Raspberry Pi with easy read and write APIs to receive and transmit data to and from the CPU. Users can use read and write commands to directly access memory mapped registers, memory and user space applications within the FPGA.
For additional ease of use and access to vast and easy to use libraries ValentF(x) implemented the use of Python within the library stack. ValentF(x) has created C to python wrappers libraries that allows users to develop their CPU/FPGA applications in Python on Linux systems on the Raspberry Pi and the BeagleBone.
Raspberry Pi SPI to FPGA Interface
The Raspberry Pi to FPGA main communication interface is the PI SPI port. The Max stable SPI clock rate that has been tested is 32-48Mhz. Based on our development experience there are some instability issues that can occur when using higher clock rates. By default the current LOGI SPI drivers runs at 48 Mhz With the current 48Mhz clock and direct communication to the FPGA the user can expect to get 4 MB/S throughput between the Raspberry Pi and the FPGA.
FPGA side communication
The wishbone bus architecture is used on the FPGA to allow multiple address mapped peripherals and modules to be accessed from the CPU. Wishbone allows for any number of wishbone peripherals to easily be attached to the system bus and can send and receive data at a rate which is limited by the communication hardware on the CPU. In order to directly communicate from the CPU to the wishbone bus a wishbone wrapper is required that translates the wishbone communication standards to the CPU host communication protocol being used. ValentF(x) currently has stable wrappers implemented that allows efficient communication between the Raspberry Pi and the BeagleBone to the FPGA.
Scalability of the LOGI Stack
The LOGI stack architecture can be used to support any future CPU host/FPGA hardware as the LOGI ecosytem evolves. The wishbone bone bus can be wrapped to support direct communication with future supported CPU hardware as needed.
Experimenting with the LOGI Stack
Users can easily begin experimentation on using the LOGI Stack by running the LOGI Apps which are installed on the pre-configured LOGI images for the Raspberry Pi and BeagleBone. The LOGI Wishbone project contain the C and Python APIs and a configured FPGA bitstream that demonstrates the usage of read/writes to registers, memory and a PWM LED core on the FPGA.
Using the C library to communicate with LOGI Bone
The LOGI tools repository also provides a C library with code to communicate and address peripherals on a wishbone architecture loaded on the LOGI Bone. This code can directly be linked with your application code.
BBB GPMC to FPGA Interface
The default interface for communication between the BBB and the FPGA is the GPMC bus. For details about operation and implementation of the GPMC bus within the AM335x processor see section 7.1 GPMC of the AM335x reference manual.
Current GPMC performance with the LOGI Drivers
The current LOGI GPMC drivers have a theoretical bandwidth of 76MB/s and measured up to 69MB/s in user space for transfer of 128KB blocks. Our kernel driver gives access to the whole address space of the FPGA with EDMA but can be re-written to be application specific and get better bandwidth. For now the overhead for switching from user-space to kernel space impacts a lot the performance, thus writing an application specific kernel driver (ours uses EDMA and burst access) with interrupt for transfer generated by the FPGA could get you close to theoretical bandwidth.
LOGI GPMC driver implementation details
Specific documentation and implementation details will be hosted on this specific LOGI GPMC driver wiki page.
Programming the FPGA from the BeagleBone
The Latest LOGI tools and images include a user space logi_loader, which loads the FPGA from the BB. The logi_loader is installed with the logi-tools when the user creates their own image or is included on the LOGI pre-configured images.
Older versions of the logi_loader used a kernel module to load the FPGA. This method was not as flexible, but was required at the time. Information regarding usage of the kernel module follows.
The template driver from the github exposes a programming interface in directory "/dev" called LOGIBone (/dev/LOGIBone). This character device writes incoming bytes to the FPGA through its serial programming interface. Loading a bitstream to the FPGA can be performed in the following ways:
- use the dd command : sudo dd if=<bitfile-path> of=/dev/LOGIBone bs=4M (ex : sudo dd if=logi_camera.bit of=/dev/LOGIBone bs=4M). The bs=4M argument is mandatory as it will force the interface to load all the configuration file in one access to the programming interface.
- use the LOGI_loader script : sudo logi_loader <bitfile-path> (ex : sudo LOGI_loader LOGI_camera.bit). Tihs script just calls the dd command with the aforementionned arguments.
The pre-configured LOGI linux images come with the driver installed and the LOGI_loader script installed by default. The device tree configuration adn driver loading must be performed prior to running the FPGA configuration.
Manually installing the LOGI Loader
The LOGI_loader script is available from the LOGI_loader/beagleBone repository. Just copy the BeagleBone directory to the BeagleBone file system and run the install script. The LOGI_loader will be installed into /usr/bin and can then be accessed globally to load bitstream files from any location by runing the command from the command line.
Process for running the LOGI Loader:
1) After booting linux image run the device tree setup script: $ sudo ./setup_device_tree.sh (only needed if the EEPROM is not configured to auto setup the device tree).
2) Run the LOGI Loader to load your FPGA bitstream file: $ sudo logi_loader "name.bit"
Board Version Changes
LOGI Bone Version 2 (R1.5.1) Change Listing
FCC and CE Compliance
The LOGI Pi design has undergone testing to meet FCC and CE certifications.
A smaller I2C GPIO expander was added to handle FPGA IO control during programming.
Micro-USB connector for Power
A Micro-USB connector was added to allow additional power to be supplied to the LOGI board in the case of high powered applications or for use as a standalone board.
Increased Flash size from 16Mbit to 32Mbit
A new SPI flash was used which increases the memory from 16Mbit to a 32Mbit.
SPI Buffer to FPGA and Flash
An IO buffer was added on the LOGI SPI pins that allow the SPI port to be isolated from the Flash chip pins when not being used for FPGA configuration. The Flash chip can then be directly accessed from the FPGA without conflicting with communication between the BeagleBone and the FPGA.