LOGI - Skeleton Editor - Project
Skeleton Editor Overview
The Skeleton editor addresses the problem of architecture top-level design (top-level refers to the part of a design that connects the FPGA IOs to the components of the architecture and the connections between the components). The design of the top-level of an architecture is usually a cumbersome process, very error prone mainly due to syntactical problems and signal/component decalaration problems. This top-level file usually consists in a list of components declaration and signal declaration and then a lot of connections. HDL editors are usually poor in features like auto-completion and background compilation. This makes it time consuming - as you usually need to synthesize the design to detect errors.
The goal of the skeleton editor is to provide a multi-platform graphical HDL editor solution, which allows users to capture the top-level of an architecture as a set of graphical components connected through grahpical signals. The skeleton editor then has the ability to generate the VHDL file that is based on this description in a clean and human readable format. Additionally the Skeleton editor generates Xilinx project files and a Makefile to allow the user to compile the design on a different machine grahpical project was created on.
Skeleton is, for now, a very early beta version of what we target to provide, but is already useful to generate the VHDL skeleton of your upcoming projects.
The LOGI-Pi specific editor can be accessed at :http://www.valentfx.com/skeleton/?board=logipi
The LOGI-Bone specific editor can be accessed at :http://www.valentfx.com/skeleton/?board=logibone
Accessing: http://www.valentfx.com/skeleton/ will open the LOGI-Pi editor (we had to make a choice ...)
Description of the Editor
- Browse button allows you to load a previously saved .json file that describes the design
- Save Button allows you to save your design as a .json file
- Export Button generates a zip package to download containing the VHDL file and additional project related files
- Components definition drop list, contains all the components supported by the editor
- Link "wire" definitions contains all the link "wire" types (wishbone bus, std_logic, std_logic_vector) that can be used to connect the components
- Large size black dots are the top-level architecture ports, they represent the IO connected to the FPGA pins
- Blue link represent wishbone bus signals
- Orange link "wire" represents std_logic type links
- Green link "wire" represents std_logic_vector links
- Colored rounded-angle represent components instantiated in the architecture. Instantiating a new component requires to click on a free spot in the editor. The created component will be of the type selected in the Component definitions list (4)
- Small black dots on components represents the port of the components. Inputs are on the left side of the component, output and inout are on the right side. To create a link between two ports (and/or port of the top level). Just click on a port and drag a link "wire" to its destination. Release when you are on the destination port. The created link will be of the type selected in the Links "wire" definition list.
- Get Memory map button allows you to see how the wishbone components are addressed in the wishbone memory address space. This memory map is generated by the editor, it will allow you to write the software part of your project and know how to address each component of the architecture. This is particularly useful if you use the python logi_hal.py file (in the logi-tools repository, python folder).
- Super Secret feature that we want to provide to users (did some one said Cloud synthesis ?)
First project with the editor
In this first project we will use the editor to create an architecture that controls the brightness of the two on-board LEDs using a PWM controller on the wishbone bus. To get started you need to make sure that you have the following :
- logi-tools installed on your raspberry-pi/beaglebone (git clone https://github.com/fpga-logi-dev/logi-tools.git on the raspberry-pi/beaglebone)
- logi-hard installed on your build machine (PC) (git clone https://github.com/fpga-logi-dev/logi-hard.git on your PC with ISE installed)
Designing the architecture
Open your web-browser at http://www.valentfx.com/skeleton/?board=logipi
1) Clean the architecture of the GPIO_0 component by clicking on it and pressing the delete key of your keyboard at the same time (as mentionned earlier its an early beta).
2) Open the "Components definitions" list and select "wishbone_pwm"
3) Click anywhere in the bottom part of the editor and fill the pop-up with the name of your pwm component (ex:PWM_0) with no spaces in the name.
4) Now you should have a new component in the window named PWM_0. To connect this component to the wishbone bus, select wishbone bus in the "Links definition" list.
5) Click on the port (black dot) named "wbs" on the Intercon_0 component and drag a link to the port named "wbs" on the PWM_0 component. Release the link to get a blue connected link.
6) Now that our PWM component is connected to the wishbone bus, we need to connect the pwm output to the LED. To do so, select std_logic_vector in the "Links definition" list. And drag a link starting from the pwm_out port of the PWM_0 component going to the LED output port of the top level.
7) After releasing the link, you should a get a series of pop-up windows :
The First window is to specify the link width. In our case we want to connect two leds, so the size of the link is "2"
The second window asks for the source port index. Our source port is of size 7 (eg:pwm_out) so we need to select what element of the port must be connected to the link. This is specified by the start index of connection and the width of the connection is inferred from the signal width. In our case we want the bits 0 and 1 of the PWM to be connected so the connection starts at index 0.
The third window asks for the target index. In our case we want to connect the LED starting at index 0. So we just enter 0.
Once its done you should be left with a green link connecting the pwm component and the LED output port.
You architecture is now complete, just click on the "Export" button and download the zip file somewhere convinient on your PC (after clicking you'll be asked for the architecture name, dust don't use spaces in that name).
Compiling the architecture using ISE
First you need to unzip the zip file in a convienient directory. The content of the zip file is the following :
- The xise file is a project to be open with Xilinx ISE.
- The .vhd file is the top-level generated from the graphical description.
- The .ucf file is the pin mapping file for your board.
- The Makefile and the other files, can be used to compile the design using Xiling tools outside the GUI (only for Linux).
Once unziped, open the .xise file with Xilinx ISE. This should result in the following error window :
This window informs you that ISE is unable to locate some of the project files. In fact the Skeleton editor has no clue of where you store your files on your PC so it generates a path for the files of the logi-hard library prefixed with a system variable (LOGI_HARD). To fix this, you just need to click on the browsing button of th efirst missing file and locate it. In this example the first missing file is logi_wishbone_pack.vhd that is located in the logi-hard/hdl/wishbone in your copy of the logi-hard repository. Once you have loacted the first file, all the other should be automatically fixed.
Once you have completed this setp, you can have a look at the generated VHDL code and then compiles it by hitting the "Generate Programming File" option.
When the tool is done synthesinzing the project you should have a .bit file in your project directory that you can copy to your raspberry-pi. You can then load the FPGA with the compiled bitsream by running the following command on your raspberry-pi :
sudo logi_loader my_project.bit
Controlling the PWM channels using python
Write the following python file
In your code you need to fix the path of the logi_hal.py file based on where you logi-tools repository copy is installed.
The PWM_0 address can be found by clicking the "Get Memory Map" button in the skeleton editor when you have finished editing your design.
The setPWMDivider method configures the pwm component to divide the main clock to generate the based clock for all the pwm channels.
The setPwmPeriod method configures the period of the pwm signal for all the channels.
The setPwmPuls method configures the period for which the pwm signal is high hence the duty cycle of the pwm.
The goal of this scipt is to generate a sinusoidal pattern on led0 and led. Because the LED of the LOGI board are low power, you may have trouble seing the actual sinus, but you'll see the led fade and rise.