The Xilinx BSDL files only cover the fpga. When you put that fpga on a PCB then you must take their file and replace their pad names with the pcd signal names that are connected to each pad on the PCB. That way the modified BSDL file maps the jtag registers to the actual PCB signal names. You can do it once and release it with the board. If not then each and every test engineer has to do it.
The end user will also modify your BSDL if they add any internal jtag user registers (The logiPi fpga has up to 4) or add a user chip_id. That BSDL covers the programmed fpga on your PCB.
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The end user will also modify your BSDL if they add any internal jtag user registers (The logiPi fpga has up to 4) or add a user chip_id. That BSDL covers the programmed fpga on your PCB.