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Configuring Logi-Bone using Non-OS environment

mhadamhada
in LOGI-Bone Discussion
Hi,

We want to configure the SPARTAN6 FPGA using Non-OS environment from BBB such as starterware.

Can some one tell us as to which is the most simple way of doing it? Again Whether SPI and I2C are the only programming interface between BBB and LB2 or is GPMC interface also used for configuring FPGA through BBB.

Comments

  • jpiatjpiat
    Hi,

    the FPGA is configured only through i2c and SPI. The I2C is used to drive a IO port expander that control the slow signals of teh configuration (init, prog, done) and the spi is used to send teh bitstream. If you have a look at the linux code for the loader, it should be fairly easy to remove all the linux related part and replace with i2c/spi code. Do starterware allow to access a filessystem where teh bitstream would be stored ? Are your using a LOGI-BONE 1.1 or 1.5 ?

    Regards,

    Jonathan Piat
    mhada
  • jpiatjpiat
    Moreover i have code to configure the GPMC (for fpga/BBB communication) that should work with starterware. Before device-tree was introduced, i was cconfigurinf teh GPMC at the register level.
    mhada
  • mhadamhada
    Hi Jpiat,

    Thanks for the reply. I am clear regarding the hardware but how to go about the program written in logi-tools is not very clear to me as I am not used to of linux but I can try [A brief document regarding the flow of the code would have been very helpful].

    When you say:- "Do starterware allow to access a filessystem where teh bitstream would be stored ?" I am not clear what you mean. I was trying to club the bitstream in form of an array with my application code, compile it and then keep in on board eMMC along with the boot image. I am using LOGI-BONE 1.5.1.

    If you can share the code of GPMC, will be very helpful, the reason why as we want to boot the BBB ultimately using a custom made NOR Cape to sit on BBB which will hold our FPGA programs. Then those FPGA programs we want to transfer to LOGI BONE V2 [To define the larger picture in brief]. This exercise will help us to design our final system.
  • jpiatjpiat
    If you pack the bitstream in your code, then it should be fine. Here is the configuration flow :

    1) Set expander GPIO directions (prog pin, mode1 and mux_oen pin as outputs others as inputs)
    2) Set mode1, prog to high, mux_oen to low and wait some µs
    3) set progb low
    4) wait for init pin to go low
    5) set progb high
    6) wait for init pin to go high
    7)) send all the bytes of the bitsream MSB first on SPI
    8) Optionnaly wait for the done pin to go high


    The pins number on the expander are sum-up in unified_loader/logi_loader.h with expander i2c address and register address. You will get info on how to communicate with the expander in unified_loader/i2c_loader.c

    The code for GPMC configuration is on the logi-kernel repository old/beaglebone/modules


    Regards,

    Jonathan Piat
    mhada
  • mhadamhada
    Hi Jonathan,

    Thanks for the response. Can you tell me as to what do you mean by mode 1. I think the mode should be set to 3 for slave serial isn't it?

    Again another confusion, I have as to INIT is first described as input and then as output bu the algo or scheme given by you tell INIT as output at all times. This confusion I have from the UG of xilinx device as well.

    If you could tell something on this.

    Many Regards...
  • jpiatjpiat
    You are rightthe configuration mode is selected through mode1 and mode0.By default mode0 is pulled to high on the board and mode1 is pulled to low to load from flash by  default. Putting mode1 high will configure mode0, mode1 at '11' which is the third mode, slave serial.

    Init is configured as input all the time, where do you see in the algo that its set to output ?

    Regards,

    Jonathan Piat
    mhada
  • mhadamhada
    I think I am confusing my question on INIT. I think you are telling input w.r.t to Expander IC I/O Port / uC port. But I am telling w.r.t. to the FPGA given in conceptual explanation given in UG380.pdf of Xilinx Slave Serial Configuration. There it tells INIT as Input of FPGA in the beginning and output thereafter for error indication.

    Now according to your flow:-

    4) wait for init pin to go low
    6) wait for init pin to go high

    i.e. INIT is an output pin of FPGA at all times. I am slightly confused with this...
  • jpiatjpiat
    When the INIT pin of the FPGA is configured as an input (FPGA side) it appears high because its pulled-up and can be read by the Master (the Bone in our case) if configured as an input on the master side.
    mhada
  • mhadamhada
    Hi Jonathan, One more query in this thread for your kind attention:-

    If I do not boot from BBB eMMC and do this programming using starterware through JTAG interface:-

    Then will setting the SPI1 interface for transfer of data and I2C1 interface for control will do the trick or do I need to consider on board EEPROM and other hardware present on Logi Bone V2. A remark on this with your experience will be helpful as we are in a hurry to prove this aspect of programming...

    Many Thanks.

    mhada..


  • jpiatjpiat
    I2C and SPI are enough to configure the FPGA. The eeprom is used by device tree when booting linux, so no need to do anything for it. Basically your bare-metal program should only initialize i2c and spi and the apply the FPGA configuration flow.
    mhada
  • mhadamhada
    Thanks a lot...
  • jpiatjpiat
    Let me know if you encounter any problem with this, i'd be happy to help debugging the code.
    mhada
  • mhadamhada
    Thanks a lot Jonathon, very kind of you...
  • mhadamhada
    Hi jonathan,

    In your previous post you have said regarding mux_oen pin. I do not find any such pin on the expander of I2C to GPIO. Which one is that you mean here?

    Again can i pull down CFG_FLSH_RST permanently so that FLASH is bypassed here?

    Regards.
  • mhadamhada
    The reason I ask this:-

    Again can i pull down CFG_FLSH_RST permanently so that FLASH is bypassed here?

    Is that I do not know as to what will happen between FLASH and FPGA in the time when I will be configuring the I2C Expander through BBB. Will the power on reset configuration of I2C expander itself help to bypass FLASH is something I am not sure.

    Regards.
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