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How to use block/burst mode with wishbone

ronyoung1ronyoung1
in LOGI Projects Discussion
Hi Everyone:

  I am almost a complete newbie when it comes to fgpa... One of the things that I want to use my logi-pi/logi-bones for is to simulate
  retro-computing. I would like to be able to load blocks of data to/from the fpga. In looking at the wishbone and virtual-components
  projects, I can see how to transfer single values using the register model. What I would like to do is to transfer a block of data to
  a block memory in the fpga using the wishbone bus.

  Would using something similar to the fifo-lib model in the virtual-components project allow me to do this?

  thanks

  -ron

Comments

  • jpiatjpiat
    Hi Ron,

    there is a wishbone_sared_mem component in the logi-hard repository that does just that. This component can be read/write from the wishbone bus but also have a read/write interface for the general logic. For the software side you can access the wishbone memory space either from python using the logi library (installed by default on the logi images) or using the c library (in logi-tools/c), to read/write block of data. When using these libraries you can specify the size of the transfer in bytes (must be 16-bit aligned). To have an example you can have a look at the logi-com-test (you should update your repository copy to see it) which have both the hardware and software components.

    Best regards,

    Jonathan Piat 
  • ronyoung1ronyoung1
    excellent....that's what I needed.

    thanks
    -ron
  • laksonobudilaksonobudi
    i am newbie want to do that, can you explain step by step? i have done with spi transfer register in my logibone. in hw side, am i just replace wishbone_register vhdl module and controll data & address?
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