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0-255 adder missing integer 17 and 19?
prolly not exactly what you were hoping for, in the way of code....
but I seem to have run out of ideas....
expected function: to send integer 0 to 255 repeatedly over uart
actual: 0 to 255 repeatedly, but missing integers 17 and 19 only.
I have built and run this a number of times, results always identical.
based on: http://hamsterworks.co.nz/mediawiki/index.php/Module_16
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top_level is
Port ( clk_50MHz : in STD_LOGIC; -- FPGA's external oscillator
data_out : out std_logic
);
end top_level;
architecture Structural of top_level is
signal busyshiftreg : std_logic_vector(9 downto 0) := (others => '0');
signal datashiftreg : std_logic_vector(9 downto 0) := (others => '1');
signal counter : std_logic_vector(12 downto 0) := (others => '0');
signal shiftreg : std_logic_vector(7 downto 0) := "00000000";
begin
data_out <= datashiftreg(0);
uart_out : process (clk_50MHz) is
begin
if rising_edge(clk_50MHz) then
if busyshiftreg(0) = '0' then
busyshiftreg <= (others => '1');
datashiftreg <= '1' & shiftreg & '0';
shiftreg <= shiftreg + 1;
elsif counter = 5207 then -- 9600 baud
datashiftreg <= '1' & datashiftreg(9 downto 1);
busyshiftreg <= '0' & busyshiftreg(9 downto 1);
counter <= (others => '0');
else
counter <= counter+1;
end if;
end if;
end process;
end Structural;
but I seem to have run out of ideas....
expected function: to send integer 0 to 255 repeatedly over uart
actual: 0 to 255 repeatedly, but missing integers 17 and 19 only.
I have built and run this a number of times, results always identical.
based on: http://hamsterworks.co.nz/mediawiki/index.php/Module_16
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top_level is
Port ( clk_50MHz : in STD_LOGIC; -- FPGA's external oscillator
data_out : out std_logic
);
end top_level;
architecture Structural of top_level is
signal busyshiftreg : std_logic_vector(9 downto 0) := (others => '0');
signal datashiftreg : std_logic_vector(9 downto 0) := (others => '1');
signal counter : std_logic_vector(12 downto 0) := (others => '0');
signal shiftreg : std_logic_vector(7 downto 0) := "00000000";
begin
data_out <= datashiftreg(0);
uart_out : process (clk_50MHz) is
begin
if rising_edge(clk_50MHz) then
if busyshiftreg(0) = '0' then
busyshiftreg <= (others => '1');
datashiftreg <= '1' & shiftreg & '0';
shiftreg <= shiftreg + 1;
elsif counter = 5207 then -- 9600 baud
datashiftreg <= '1' & datashiftreg(9 downto 1);
busyshiftreg <= '0' & busyshiftreg(9 downto 1);
counter <= (others => '0');
else
counter <= counter+1;
end if;
end if;
end process;
end Structural;
Comments
nothing is output to console, see end for edited copy
all other integers are present.
.ucf
NET "clk_50MHz" LOC = P85; #50Mhz
NET "data_out" LOC = P82; #TX
read_uart:
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#include <fcntl.h>
#include <errno.h>
#include <termios.h>
int main(int argc, char ** argv) {
int fd;
struct termios options;
tcgetattr(fd, &options);
cfsetispeed(&options, B9600); //B115200);
cfsetospeed(&options, B9600); //B115200);
tcflush(fd, TCIFLUSH);
tcsetattr(fd, TCSANOW, &options);
// Open the Port. We want read/write, no "controlling tty" status, and open it no matter what state DCD is in
fd = open("/dev/ttyAMA0", O_RDONLY | O_NOCTTY | O_NDELAY);
if (fd == -1) {
perror("open_port: Unable to open /dev/ttyAMA0 - ");
return(-1);
}
// Turn off blocking for reads, use (fd, F_SETFL, FNDELAY) if you want that
fcntl(fd, F_SETFL, 0);
char buffer[1];
while(1) {
int n = read(fd, (void*)buffer, 1);
if (n < 0) {
perror("Read failed - ");
return -1;
} else if (n == 0) printf("."); //printf("No data on port\n");
else {
buffer[n] = '\0';
printf("%d\n",buffer[0]);
fflush(stdout);
}
}
close(fd);
return 0;
}
254
255
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
20
21
22
23
wfm
see: http://en.m.wikipedia.org/wiki/Software_flow_control
I did not yet find a way using termios
courtesy Hamsterworks!
tx
~:"
tx
~:"