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Logibone GPMC(AAD) to WBM interface

jcdeveljcdevel
in LOGI-Bone Discussion
Hi Experts,

I have been working on a GPMC(AAD) to Wishbone interface module to extend the addressing space. I have a prototype working in synchronous mode with optional burst capability. I would like to contribute it to the project but I could not find any guide in the Wiki or the Forums (I apologize if I missed it). Is there a patch review process? How could I submit my modules? Github PR?

Thanks,
JC

Comments

  • jpiatjpiat
    Great news ! Did you make it wotk using our wishbone wrapper as a base or did you write it from scratch ? One possibility could be to had your module to the repository or try to make the existing wrapper generic with th option for AAD instead of AD.
  • jcdeveljcdevel
    Hello Jonathan,

    I used the wishbone wrapper as a reference, but the implementation is quite different, so I do not think we can merge both modules in a generic wrapper. Good news is that the interface is compatible with the standard wishbone wrapper, so just adding an _aad suffix to the component instance in the top module will do it (and of course adjust the address bus width). Maybe I can fork the logi-hard repo on Github and push my branch there so you can review it? I can also provide the kernel patches to the GPMC driver and device tree (they are based on v3.14).

    Thanks,
    JC
  • jpiatjpiat
    Forking then requesting a pull seems like a good way to proceed. For the kernel patches this will be more difficult to distribute, but we can set a up a patches folder somewhere on the repository for advanced users.
  • jcdeveljcdevel
    I am running some more tests before pushing externally, just to make sure that everything is working as expected. I should have something ready in a couple of days (hopefully). I will let you know.

    Thanks,
    JC
  • jcdeveljcdevel
    I am having some trouble implementing the write operation in burst mode. I think it is a timing issue but it is hard to say because I do not have a logic analyzer or any equipment to check the signals in the GPMC bus. I am going to double check the timing constrains in the project. I will keep you updated.

    Thanks,
    JC
    mjones
  • jcdeveljcdevel
    Sorry it took so long, but I had to rework the module completely as I could not get it pass the stress tests I wrote. Now it is finally working and I have sent the pull-request on Github. Feedback/suggestions are welcome.

    https://github.com/fpga-logi/logi-hard/pull/4

    Thanks,
    JC
  • LiukaFinkeLiukaFinke
    Can you please share the your whole system here?
    What hardware yo are using, can you please share the specifications of each and every component?
    Also please share the full details of your modules.
    Try to upload the Firmware if you can.
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